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[Qemu-devel] [PATCH v2 4/6] hw/riscv/virt: Connect a VGA PCIe device
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 4/6] hw/riscv/virt: Connect a VGA PCIe device |
Date: |
Mon, 9 Jul 2018 17:28:36 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
hw/riscv/virt.c | 7 ++++++-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index 2c943e2669..fcefa68f1e 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak
b/default-configs/riscv64-softmmu.mak
index 2c943e2669..fcefa68f1e 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0c3800fd64..f973c43c70 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -322,6 +322,8 @@ static void riscv_virt_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ PCIBus *pci_bus;
+ DeviceState *dev;
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -437,9 +439,12 @@ static void riscv_virt_board_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
}
- gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+ dev = gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ pci_vga_init(pci_bus);
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
--
2.17.1
- [Qemu-devel] [PATCH v2 0/6] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/07/09
- [Qemu-devel] [PATCH v2 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/07/09
- [Qemu-devel] [PATCH v2 2/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/07/09
- [Qemu-devel] [PATCH v2 3/6] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/07/09
- [Qemu-devel] [PATCH v2 4/6] hw/riscv/virt: Connect a VGA PCIe device,
Alistair Francis <=
- [Qemu-devel] [PATCH v2 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/07/09
- [Qemu-devel] [PATCH v2 6/6] riscv64-softmmu.mak: Build Virtio Block support, Alistair Francis, 2018/07/09