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[Qemu-devel] [PATCH v1 0/4] RISC-V: Populate mtval and stval
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 0/4] RISC-V: Populate mtval and stval |
Date: |
Wed, 25 Jul 2018 16:03:35 -0700 |
Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.
Alistair Francis (4):
target/riscv: Rename mbadaddr and sbadaddr
target/riscv: Implement the mtval illegal instruction
target/riscv: Implement the stval illegal instruction
target/riscv: set mtval and stval support
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 8 +++++---
target/riscv/cpu_bits.h | 4 ++--
target/riscv/helper.c | 34 ++++++++++++++++++++++++++--------
target/riscv/op_helper.c | 16 ++++++++--------
target/riscv/translate.c | 12 ++++++++++++
6 files changed, 57 insertions(+), 21 deletions(-)
--
2.17.1
- [Qemu-devel] [PATCH v1 0/4] RISC-V: Populate mtval and stval,
Alistair Francis <=