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[Qemu-devel] [PATCH v8 13/87] target/mips: Check ELPA flag only in some
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v8 13/87] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 |
Date: |
Mon, 13 Aug 2018 19:52:38 +0200 |
From: Yongbok Kim <address@hidden>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 219de72..6740764 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4938,12 +4938,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4954,6 +4953,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -5006,12 +5006,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -5023,6 +5022,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
- [Qemu-devel] [PATCH v8 33/87] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, (continued)
- [Qemu-devel] [PATCH v8 33/87] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 31/87] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 22/87] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 34/87] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 47/87] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 53/87] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 40/87] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 07/87] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 24/87] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 19/87] qemu-doc: Amend MIPS-related items, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 13/87] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v8 18/87] linux-user: Add preprocessor availability control to some syscalls, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 27/87] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 30/87] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 20/87] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 46/87] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 37/87] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 29/87] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 36/87] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0), Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 38/87] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 55/87] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Aleksandar Markovic, 2018/08/13