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[Qemu-devel] [PATCH v9 04/84] target/mips: Mark switch fallthroughs with
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v9 04/84] target/mips: Mark switch fallthroughs with interpretable comments |
Date: |
Thu, 16 Aug 2018 16:56:57 +0200 |
From: Aleksandar Markovic <address@hidden>
Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.
The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.
The comment must be just before next "case", otherwise gcc won't
understand it.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b944ea2..3dd66b6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -14290,8 +14290,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case SDP:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWP:
case SWP:
gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -14301,8 +14301,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case SDM:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- /* Fallthrough */
#endif
+ /* fall through */
case LWM32:
case SWM32:
gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -20087,6 +20087,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_MTHC1:
check_cp1_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
+ /* fall through */
case OPC_MFC1:
case OPC_CFC1:
case OPC_MTC1:
--
2.7.4
- Re: [Qemu-devel] [PATCH v9 08/84] target/mips: Implement CP0 Config1.WR bit functionality, (continued)
- [Qemu-devel] [PATCH v9 21/84] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 02/84] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 28/84] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 17/84] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 14/84] linux-user: Add preprocessor availability control to some syscalls, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 22/84] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 04/84] target/mips: Mark switch fallthroughs with interpretable comments,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v9 03/84] target/mips: Avoid case statements formulated by ranges - part 2, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 15/84] qemu-doc: Amend MIPS-related items, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 13/84] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 35/84] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control, Aleksandar Markovic, 2018/08/16