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[Qemu-devel] [PULL 2/8] i386: Add new MSR indices for IA32_PRED_CMD and
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 2/8] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES |
Date: |
Thu, 16 Aug 2018 22:33:54 -0300 |
From: Robert Hoo <address@hidden>
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c18863ec7a..b5c6686fe2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -354,6 +354,8 @@ typedef enum X86Seg {
#define MSR_TSC_ADJUST 0x0000003b
#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_VIRT_SSBD 0xc001011f
+#define MSR_IA32_PRED_CMD 0x49
+#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 2/8] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES,
Eduardo Habkost <=
- [Qemu-devel] [PULL 3/8] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 1/8] docs: add guidance on configuring CPU models for x86, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 4/8] i386: Add CPUID bit for PCONFIG, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 5/8] i386: Add CPUID bit for WBNOINVD, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 7/8] target-i386: adds PV_SEND_IPI CPUID feature bit, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 6/8] i386: Add new CPU model Icelake-{Server, Client}, Eduardo Habkost, 2018/08/16
- [Qemu-devel] [PULL 8/8] i386: Disable TOPOEXT by default on "-cpu host", Eduardo Habkost, 2018/08/16
- Re: [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, Peter Maydell, 2018/08/17
- Re: [Qemu-devel] [PULL 0/8] x86 queue, 2018-08-16, no-reply, 2018/08/17