Re: [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control

[Aleksandar Markovic]

> > I think some of the previously-implemented similar cases involving 
> > read-only bits were handled the same way, and we just built on that. What 
> > would you suggest as a more appropriate solution in such cases (of 
> > accessing "preset by hardware" bits)?
>
> Well, ctx->insn_flags and ctx->CP0_Config1 are good examples.
> These are 100% read-only and fixed at cpu instantiation.
> 
> I see that CP0_Config3 has one writable bit for micromips, but
> is fully readonly for nanomips.  Therefore XNP and MT need not
> be copied to hflags because they will never vary.
> 
> I'd suggest copying CP0_Config3 to ctx as with Config1.
>
>
> r~

Hi, Richard,

The opinion within the team is that we should leave such changes for follow-up 
clean-up - clean-up of CP0-related functionalities is scheduled anyway soon.

The reason is that the current implementation (in v9) works fine, and this is 
very late in our dev cycle to change features with no observed bugs.

All other your concerns will be addressed in v10, which is planned to be sent 
soon.

Yours,
Aleksandar