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[Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control |
Date: |
Tue, 21 Aug 2018 14:35:32 +0200 |
From: Aleksandar Rikalo <address@hidden>
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 45 +++++++++++++++++++++++++++++++++++++--------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cd7e16c..480d4bf 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1927,6 +1927,35 @@ static inline void check_xnp(DisasContext *ctx)
}
}
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config3 MT bit is NOT set.
+ */
+static inline void check_mt(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
+/*
+ * This code generates a "coprocessor unusable" exception if CP0 is not
+ * available, and, if that is not the case, generates a "reserved instruction"
+ * exception if the Config5 MT bit is NOT set. This is needed for availability
+ * control of some of MT ASE instructions.
+ */
+static inline void check_cp0_mt(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
+ generate_exception_err(ctx, EXCP_CpU, 0);
+ } else {
+ if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
+ generate_exception_err(ctx, EXCP_RI, 0);
+ }
+ }
+}
+
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
@@ -8595,7 +8624,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc, int rt,
opn = "mthc0";
break;
case OPC_MFTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
if (rd == 0) {
/* Treat as NOP. */
return;
@@ -8605,7 +8634,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc, int rt,
opn = "mftr";
break;
case OPC_MTTR:
- check_insn(ctx, ASE_MT);
+ check_cp0_enabled(ctx);
gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
opn = "mttr";
@@ -21960,7 +21989,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
break;
case OPC_FORK:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -21973,7 +22002,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case OPC_YIELD:
- check_insn(ctx, ASE_MT);
+ check_mt(ctx);
{
TCGv t0 = tcg_temp_new();
@@ -23270,22 +23299,22 @@ static void decode_opc(CPUMIPSState *env,
DisasContext *ctx)
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EMT:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_emt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
- check_insn(ctx, ASE_MT);
+ check_cp0_mt(ctx);
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
break;
--
2.7.4
- [Qemu-devel] [PULL 00/46] MIPS queue August 21, 2018, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 09/46] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 03/46] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 12/46] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 06/46] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 07/46] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 01/46] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 27/46] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/21
- [Qemu-devel] [PULL 10/46] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/21