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[Qemu-devel] [PULL v5 24/46] target/mips: Add CP0 Config3 and Config5 fi
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v5 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure |
Date: |
Thu, 23 Aug 2018 16:18:39 +0200 |
From: Dimitrije Nikolic <address@hidden>
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.
Reviewed-by: "Aleksandar Markovic <address@hidden>"
Signed-off-by: "Aleksandar Markovic <address@hidden>"
---
target/mips/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4b1bb18..10475a6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1449,6 +1449,8 @@ typedef struct DisasContext {
uint32_t opcode;
int insn_flags;
int32_t CP0_Config1;
+ int32_t CP0_Config3;
+ int32_t CP0_Config5;
/* Routine used to access memory */
int mem_idx;
TCGMemOp default_tcg_memop_mask;
@@ -23307,6 +23309,8 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
ctx->CP0_Config1 = env->CP0_Config1;
+ ctx->CP0_Config3 = env->CP0_Config3;
+ ctx->CP0_Config5 = env->CP0_Config5;
ctx->btarget = 0;
ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
--
2.7.4
- [Qemu-devel] [PULL v5 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, (continued)
- [Qemu-devel] [PULL v5 04/46] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 01/46] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 13/46] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 03/46] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 06/46] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 08/46] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 12/46] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v5 05/46] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 42/46] elf: Don't check FCR31_NAN2008 bit for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 02/46] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 15/46] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 23/46] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 20/46] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v5 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/23