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[Qemu-devel] [PATCH v4 7/7] hw/riscv/virt: Connect a VirtIO net PCIe dev
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v4 7/7] hw/riscv/virt: Connect a VirtIO net PCIe device |
Date: |
Wed, 29 Aug 2018 10:57:25 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/virt.c | 20 +++++++++++++++++---
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak
b/default-configs/riscv64-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d360d66e42..faca8e3d42 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "chardev/char.h"
+#include "net/net.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
@@ -322,6 +323,8 @@ static void riscv_virt_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ DeviceState *dev;
+ PCIBus *pci_bus;
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -436,9 +439,20 @@ static void riscv_virt_board_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
}
- gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
- memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
- qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+ dev = gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+ memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
+ qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
--
2.17.1
- [Qemu-devel] [PATCH v4 0/7] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 1/7] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 2/7] hw/riscv/spike: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 3/7] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 4/7] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 5/7] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 6/7] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/08/29
- [Qemu-devel] [PATCH v4 7/7] hw/riscv/virt: Connect a VirtIO net PCIe device,
Alistair Francis <=