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Re: [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support
From: |
Aleksandar Markovic |
Subject: |
Re: [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support |
Date: |
Thu, 30 Aug 2018 12:40:07 +0000 |
Hi, Craig,
> From: Craig Janeczek <address@hidden>
> Sent: Tuesday, August 28, 2018 3:00 PM
>
> Subject: [PATCH v3 0/8] Add limited MXU instruction support
>
> This patch set begins to add MXU instruction support for mips emulation.
Based on the info I have, I think a reasonable approach to integration of this
series would be:
- Add this line in mips-defs.h
#define ASE_MXU 0x02000000
- In main switch, use this segment
if (ctx->insn_flags & ASE_MXU) {
decode_opc_special2_mxu(env, ctx);
} else {
decode_opc_special2_legacy(env, ctx);
}
That way, you would be able to add MXU code without specifying CPU that
supports it. This will enable you to focus on MXU, which is a serieoous task
anyway. Hopefully, a CPU will be added at some later date.
Thanks,
Aleksandar
- Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes, (continued)
[Qemu-devel] [PATCH v3 1/8] target/mips: Introduce MXU registers, Craig Janeczek, 2018/08/28
[Qemu-devel] [PATCH v3 7/8] target/mips: Add MXU instructions Q8MUL and Q8MULSU, Craig Janeczek, 2018/08/28
[Qemu-devel] [PATCH v3 5/8] target/mips: Add MXU instruction D16MUL, Craig Janeczek, 2018/08/28
[Qemu-devel] [PATCH v3 8/8] target/mips: Add MXU instructions S32LDD and S32LDDR, Craig Janeczek, 2018/08/28
Re: [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support, Aleksandar Markovic, 2018/08/29
Re: [Qemu-devel] [PATCH v3 0/8] Add limited MXU instruction support,
Aleksandar Markovic <=