[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [Question] Question about the i440FX device
From: |
Li Qiang |
Subject: |
Re: [Qemu-devel] [Question] Question about the i440FX device |
Date: |
Mon, 10 Sep 2018 09:22:34 +0800 |
Thanks Paolo,
Paolo Bonzini <address@hidden> 于2018年9月10日周一 上午7:11写道:
> On 07/09/2018 08:32, Li Qiang wrote:
> > Hello all,
> >
> > I want to know why the i440FX in the following 'info qtree' information
> is
> > laid under the pci.0 bus. In the chip spec here:
> > -->https://wiki.qemu.org/images/b/bb/29054901.pdf
> > I don't see this device.
> >
> > Can anyone give me some hints?
>
> Hi,
>
> the device implements what is in "3.2. PCI Configuration Space Mapped
> Registers" in the i440FX spec.
>
>
Indeed, also I find the comments in 'i440fx_class_init' is useful.
As I got the 'PCII440FXState' is for the "PCI-facing part of the host
bridge"
and 'I440FXState' is for the "host-facing part".
Thanks,
Li Qiang
> Paolo
>