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[Qemu-devel] [PATCH v4 0/8] target/mips: Support R5900 GCC programs in u
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v4 0/8] target/mips: Support R5900 GCC programs in user mode |
Date: |
Sun, 16 Sep 2018 20:32:54 +0200 |
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo. In particular, this avoids issues with cross compilation.
This change has been tested with Gentoo compiled for R5900, including
native compilation of several packages under QEMU.
The R5900 implements the 64-bit MIPS III instruction set except DMULT,
DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN,
MOVZ and PREF are implemented. It has the R5900 specific three-operand
instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions
MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and
MTLO1. A set of 93 128-bit multimedia instructions specific to the
R5900 is also implemented.
The Toshiba TX System RISC TX79 Core Architecture manual describes the
R5900 processor:
http://www.lukasz.dk/files/tx79architecture.pdf
Fredrik Noring (8):
target/mips: Define R5900 instructions and CPU preprocessor constants
target/mips: Support R5900 specific three-operand MULT and MULTU
target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV
target/mips: Add function to signal RI exception unless user only
target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only
target/mips: Define the R5900 CPU
linux-user/mips: Recognise the R5900 CPU model
elf: Toshiba/Sony rather than MIPS are the implementors of the R5900
include/elf.h | 2 +-
linux-user/mips/target_elf.h | 3 ++
target/mips/mips-defs.h | 2 +
target/mips/translate.c | 80 ++++++++++++++++++++++++++++++++++++++--
target/mips/translate_init.inc.c | 47 +++++++++++++++++++++++
5 files changed, 130 insertions(+), 4 deletions(-)
--
2.16.4
- [Qemu-devel] [PATCH v4 0/8] target/mips: Support R5900 GCC programs in user mode,
Fredrik Noring <=
- [Qemu-devel] [PATCH v4 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Philippe Mathieu-Daudé, 2018/09/16