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Re: [Qemu-devel] [PATCH v5 2/3] target/s390x: exception on non-aligned L
From: |
David Hildenbrand |
Subject: |
Re: [Qemu-devel] [PATCH v5 2/3] target/s390x: exception on non-aligned LPSW(E) |
Date: |
Tue, 18 Sep 2018 09:53:03 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
Am 02.09.18 um 02:33 schrieb Pavel Zbitskiy:
> Both LPSW and LPSWE should raise a specification exception when their
> operand is not doubleword aligned.
>
> Signed-off-by: Pavel Zbitskiy <address@hidden>
> ---
> target/s390x/translate.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index 7363aabf3a..59b1e5893c 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -2835,7 +2835,8 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps
> *o)
>
> t1 = tcg_temp_new_i64();
> t2 = tcg_temp_new_i64();
> - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
> + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
> + MO_TEUL | MO_ALIGN_8);
> tcg_gen_addi_i64(o->in2, o->in2, 4);
> tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
> /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
> @@ -2855,7 +2856,8 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps
> *o)
>
> t1 = tcg_temp_new_i64();
> t2 = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
> + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
> + MO_TEQ | MO_ALIGN_8);
> tcg_gen_addi_i64(o->in2, o->in2, 8);
> tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
> gen_helper_load_psw(cpu_env, t1, t2);
>
Reviewed-by: David Hildenbrand <address@hidden>
Thanks!
--
Thanks,
David / dhildenb
- [Qemu-devel] [PATCH v5 0/3] Some improvements in z/Arch instructions support, Pavel Zbitskiy, 2018/09/01
- [Qemu-devel] [PATCH v5 1/3] target/s390x: use regular spaces in translate.c, Pavel Zbitskiy, 2018/09/01
- [Qemu-devel] [PATCH v5 2/3] target/s390x: exception on non-aligned LPSW(E), Pavel Zbitskiy, 2018/09/01
- Re: [Qemu-devel] [PATCH v5 2/3] target/s390x: exception on non-aligned LPSW(E),
David Hildenbrand <=
- [Qemu-devel] [PATCH v5 3/3] target/s390x: implement CVB, CVBY and CVBG, Pavel Zbitskiy, 2018/09/01
- Re: [Qemu-devel] [PATCH v5 0/3] Some improvements in z/Arch instructions support, David Hildenbrand, 2018/09/02