Re: [Qemu-devel] [PATCH 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties

[Peter Maydell]

On 31 August 2018 at 11:38, Cédric Le Goater <address@hidden> wrote:
> The setting of the DRAM address of the DMA transaction depends on the
> DRAM base address and the maximun DRAM size of the SoC. Let's add a
> couple of properties to give this information to the SMC controller
> model.

In hardware, does the SMC controller really know the base address
of DRAM, or is it actually emitting transactions that the
bus fabric in the SoC sends to the right place? That is, would
it be more accurate to model it by passing the SMC controller a
MemoryRegion to use for emitting DMA transactions which was an
alias into the right part of the address space ?

thanks
-- PMM