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[Qemu-devel] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum |
Date: |
Fri, 21 Sep 2018 18:19:38 +0200 |
Emulate read errors in the DMA Checksum Register for high frequencies
and optimistic settings of the Read Timing Compensation Register. This
will help in tuning the SPI timing calibration algorithm.
The values below are those to expect from the first flash device of
the FMC controller of a palmetto-bmc machine.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/ssi/aspeed_smc.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index db89c54dfc9f..01c3fd7b2666 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -751,6 +751,30 @@ static void aspeed_smc_dma_calibration(AspeedSMCState *s)
s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
}
+static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
+{
+ uint8_t delay =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
+ uint8_t hclk_mask =
+ (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
+
+ /*
+ * Typical values of a palmetto-bmc machine.
+ */
+ switch (aspeed_smc_hclk_divisor(hclk_mask)) {
+ case 4 ... 16:
+ return false;
+ case 3: /* at least one HCLK cycle delay */
+ return (delay & 0x7) < 1;
+ case 2: /* at least two HCLK cycle delay */
+ return (delay & 0x7) < 2;
+ case 1: /* (> 100MHz) is above the max freq of the controller */
+ return true;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/*
* Accumulate the result of the reads to provide a checksum that will
* be used to validate the read timing settings.
@@ -788,6 +812,11 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
s->regs[R_DMA_FLASH_ADDR] += 4;
s->regs[R_DMA_LEN] -= 4;
}
+
+ if (aspeed_smc_inject_read_failure(s)) {
+ s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
+ }
+
}
static void aspeed_smc_dma_rw(AspeedSMCState *s)
--
2.17.1
- [Qemu-devel] [PATCH v2 00/11] aspeed: misc fixes and enhancements (SMC), Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 01/11] aspeed/timer: fix compile breakage with clang 3.4.2, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 02/11] hw/arm/aspeed: change the FMC flash model of the AST2500 evb, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 03/11] hw/arm/aspeed: Add an Aspeed machine class, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 04/11] hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 05/11] aspeed/smc: fix some alignment issues, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 06/11] aspeed/smc: fix default read value, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 11/11] aspeed/smc: Add dummy data register, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 10/11] aspeed/smc: inject errors in DMA checksum,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v2 08/11] aspeed/smc: add support for DMAs, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 09/11] aspeed/smc: add DMA calibration settings, Cédric Le Goater, 2018/09/21
- [Qemu-devel] [PATCH v2 07/11] aspeed/smc: add a 'sdram_base' and 'max-ram-size' properties, Cédric Le Goater, 2018/09/21
- Re: [Qemu-devel] [PATCH v2 00/11] aspeed: misc fixes and enhancements (SMC), Peter Maydell, 2018/09/25