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Re: [Qemu-devel] [PATCH 01/13] target/arm: Add ARM_FEATURE_SWP
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 01/13] target/arm: Add ARM_FEATURE_SWP |
Date: |
Tue, 25 Sep 2018 10:49:33 +0100 |
On 16 September 2018 at 16:53, Richard Henderson
<address@hidden> wrote:
> Ah, I did not know about SWP_EMULATE. It appears to be
> specific to armv7+ (though we don't support the pre-v4
> cpus for which it might otherwise be relevant).
>
> It does appear that HWCAP_SWP is advertised anyway:
>
> mm/proc-v7.S: .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT
I just discovered that that is overridden by
arch/arm/kernel/setup.c:elf_hwcap_fixup(), which looks at the
ID registers and suppresses HWCAP_SWP if LDREX/STREX and LDREXB/STREXB
are supported.
(Compat 32-bit support in a 64-bit kernel never advertises
HWCAP_SWP.)
thanks
-- PMM
- [Qemu-devel] [RFC PATCH 00/13] target/arm: Derive cpu id regs from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 02/13] target/arm: Derive id_isar0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 03/13] target/arm: Derive id_isar1 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 05/13] target/arm: Derive id_isar3 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 06/13] target/arm: Derive id_isar4 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 04/13] target/arm: Derive id_isar2 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 08/13] target/arm: Derive id_pfr0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 07/13] target/arm: Derive id_isar5 and id_isar6 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 09/13] target/arm: Derive id_pfr1 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 10/13] target/arm: Derive id_aa64isar0 from features, Richard Henderson, 2018/09/15
- [Qemu-devel] [PATCH 11/13] target/arm: Derive id_aa64isar1 from features, Richard Henderson, 2018/09/15