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Re: [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV |
Date: |
Sun, 30 Sep 2018 17:16:13 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 9/15/18 10:43 AM, Fredrik Noring wrote:
> The R5900 is taken to be MIPS III with certain modifications. From
> MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Again, you can keep R-b tag for simple rewording.
>
> Signed-off-by: Fredrik Noring <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/mips/translate.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 7e18ec0d03..0c445c11c5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -22422,7 +22422,7 @@ static void decode_opc_special_legacy(CPUMIPSState
> *env, DisasContext *ctx)
> case OPC_MOVN: /* Conditional move */
> case OPC_MOVZ:
> check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
> - INSN_LOONGSON2E | INSN_LOONGSON2F);
> + INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
> gen_cond_move(ctx, op1, rd, rs, rt);
> break;
> case OPC_MFHI: /* Move from HI/LO */
> @@ -25006,7 +25006,8 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> break;
> case OPC_PREF:
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
> + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
> + INSN_R5900);
> /* Treat as NOP. */
> break;
>
>
- [Qemu-devel] [PATCH v6 0/7] target/mips: Limited support for the R5900, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 1/7] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 2/7] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 5/7] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 4/7] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/29
- Re: [Qemu-devel] [PATCH v6 3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v6 7/7] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/29
- [Qemu-devel] [PATCH v6 6/7] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/29