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[Qemu-devel] [PATCH v3 05/15] target/arm: Adjust aarch64_cpu_dump_state
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 05/15] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE |
Date: |
Fri, 5 Oct 2018 12:53:40 -0500 |
Use the existing helpers to determine if (1) the fpu is enabled,
(2) sve state is enabled, and (3) the current sve vector length.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 4 ++++
target/arm/helper.c | 6 +++---
target/arm/translate-a64.c | 8 ++++++--
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a4ee83dc77..da4d3888ea 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -920,6 +920,10 @@ target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
+int fp_exception_el(CPUARMState *env, int cur_el);
+int sve_exception_el(CPUARMState *env, int cur_el);
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
+
static inline bool is_a64(CPUARMState *env)
{
return env->aarch64;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b8d838dbc..a3a3b9672c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4406,7 +4406,7 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
* take care of raising that exception.
* C.f. the ARM pseudocode function CheckSVEEnabled.
*/
-static int sve_exception_el(CPUARMState *env, int el)
+int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1) {
@@ -4464,7 +4464,7 @@ static int sve_exception_el(CPUARMState *env, int el)
/*
* Given that SVE is enabled, return the vector length for EL.
*/
-static uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t zcr_len = cpu->sve_max_vq - 1;
@@ -12547,7 +12547,7 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,
uint32_t bytes)
/* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
-static int fp_exception_el(CPUARMState *env, int cur_el)
+int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
int fpen;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8ca3876707..8a24278d79 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -166,11 +166,15 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "\n");
return;
}
+ if (fp_exception_el(env, el) != 0) {
+ cpu_fprintf(f, " FPU disabled\n");
+ return;
+ }
cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
- if (arm_feature(env, ARM_FEATURE_SVE)) {
- int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
+ if (arm_feature(env, ARM_FEATURE_SVE) && sve_exception_el(env, el) == 0) {
+ int j, zcr_len = sve_zcr_len_for_el(env, el);
for (i = 0; i <= FFR_PRED_NUM; i++) {
bool eol;
--
2.17.1
- [Qemu-devel] [PATCH v3 00/15] target/arm: sve system mode patches, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 01/15] target/arm: Define ID_AA64ZFR0_EL1, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 02/15] target/arm: Adjust sve_exception_el, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 03/15] target/arm: Pass in current_el to fp and sve_exception_el, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 04/15] target/arm: Handle SVE vector length changes in system mode, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 05/15] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 08/15] target/arm: Rewrite helper_sve_ld[234]*_r, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 07/15] target/arm: Rewrite helper_sve_ld1*_r using pages, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 06/15] target/arm: Clear unused predicate bits for LD1RQ, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 09/15] target/arm: Rewrite helper_sve_st[1234]*_r, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 10/15] target/arm: Split contiguous loads for endianness, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 11/15] target/arm: Split contiguous stores for endianness, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 12/15] target/arm: Rewrite vector gather loads, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 13/15] target/arm: Rewrite vector gather stores, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 14/15] target/arm: Rewrite vector gather first-fault loads, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 15/15] target/arm: Pass TCGMemOpIdx to sve memory helpers, Richard Henderson, 2018/10/05