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[Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4 |
Date: |
Wed, 10 Oct 2018 16:37:33 -0400 |
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d6501de1ba..89ceb34cb9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1706,7 +1706,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_W, .type = ARM_CP_NOP },
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
- * follow (although we don't actually implement any counters)
+ * follow.
*
* Performance registers fall into three categories:
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
@@ -5412,8 +5412,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement only the cycle
- * count register.
+ * field as main ID register, and we implement four counters in
+ * addition to the cycle count register.
*/
unsigned int i, pmcrn = 4;
ARMCPRegInfo pmcr = {
@@ -5430,7 +5430,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
--
2.19.1
- Re: [Qemu-devel] [PATCH v6 03/14] migration: Add post_save function to VMStateDescription, (continued)
[Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4,
Aaron Lindsay <=
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Richard Henderson, 2018/10/16
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/10/17
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Richard Henderson, 2018/10/17
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/10/17
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Richard Henderson, 2018/10/17
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Peter Maydell, 2018/10/18
- Re: [Qemu-devel] [PATCH v6 12/14] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/10/18
[Qemu-devel] [PATCH v6 14/14] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/10/10
[Qemu-devel] [PATCH v6 11/14] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/10/10