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[Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decod
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree |
Date: |
Sat, 20 Oct 2018 09:14:34 +0200 |
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
v1 -> v2:
- RISCV32 now returns false instead of raising an exception
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 68 +++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f27bdab245..5d3d2a25ac 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -195,3 +195,9 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index 3f806b8238..bd79ef96f8 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,71 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a, uint32_t insn)
return true;
}
+
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+ return true;
+#else
+ return false;
+#endif
+}
--
2.19.1
- Re: [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext, (continued)
[Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree,
Bastian Koppelmann <=
[Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/20
[Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20