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[Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 in
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass |
Date: |
Sun, 21 Oct 2018 17:36:54 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 36 +++++++++++++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c8080844f1..28137cdaf4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24459,6 +24459,38 @@ static void decode_tx79_mmi0(CPUMIPSState *env,
DisasContext *ctx)
}
}
+static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI1(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI1_PABSW: /* TODO: TX79_MMI1_PABSW */
+ case TX79_MMI1_PCEQW: /* TODO: TX79_MMI1_PCEQW */
+ case TX79_MMI1_PMINW: /* TODO: TX79_MMI1_PMINW */
+ case TX79_MMI1_PADSBH: /* TODO: TX79_MMI1_PADSBH */
+ case TX79_MMI1_PABSH: /* TODO: TX79_MMI1_PABSH */
+ case TX79_MMI1_PCEQH: /* TODO: TX79_MMI1_PCEQH */
+ case TX79_MMI1_PMINH: /* TODO: TX79_MMI1_PMINH */
+ case TX79_MMI1_PCEQB: /* TODO: TX79_MMI1_PCEQB */
+ case TX79_MMI1_PADDUW: /* TODO: TX79_MMI1_PADDUW */
+ case TX79_MMI1_PSUBUW: /* TODO: TX79_MMI1_PSUBUW */
+ case TX79_MMI1_PEXTUW: /* TODO: TX79_MMI1_PEXTUW */
+ case TX79_MMI1_PADDUH: /* TODO: TX79_MMI1_PADDUH */
+ case TX79_MMI1_PSUBUH: /* TODO: TX79_MMI1_PSUBUH */
+ case TX79_MMI1_PEXTUH: /* TODO: TX79_MMI1_PEXTUH */
+ case TX79_MMI1_PADDUB: /* TODO: TX79_MMI1_PADDUB */
+ case TX79_MMI1_PSUBUB: /* TODO: TX79_MMI1_PSUBUB */
+ case TX79_MMI1_PEXTUB: /* TODO: TX79_MMI1_PEXTUB */
+ case TX79_MMI1_QFSRV: /* TODO: TX79_MMI1_QFSRV */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI1 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI1");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24467,6 +24499,9 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
case TX79_MMI_CLASS_MMI0:
decode_tx79_mmi0(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI1:
+ decode_tx79_mmi1(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
@@ -24481,7 +24516,6 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
- case TX79_MMI_CLASS_MMI1: /* TODO: TX79_MMI_CLASS_MMI1 */
case TX79_MMI_CLASS_MMI3: /* TODO: TX79_MMI_CLASS_MMI3 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
--
2.18.1
- [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, (continued)
- [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/10/21