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[Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT |
Date: |
Mon, 22 Oct 2018 14:57:46 +0200 |
From: Fredrik Noring <address@hidden>
Add a test for MULT.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tests/tcg/mips/mipsr5900/Makefile | 25 +++++++++++++++++++++
tests/tcg/mips/mipsr5900/mult.c | 47 +++++++++++++++++++++++++++++++++++++++
2 files changed, 72 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/Makefile
create mode 100644 tests/tcg/mips/mipsr5900/mult.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg/mips/mipsr5900/Makefile
new file mode 100644
index 0000000..6757168
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -0,0 +1,25 @@
+-include ../../config-host.mak
+
+CROSS=mipsr5900el-unknown-linux-gnu-
+
+SIM=qemu-mipsel
+SIM_FLAGS=-cpu R5900
+
+CC = $(CROSS)gcc
+CFLAGS = -Wall -mabi=32 -march=r5900 -static
+
+TESTCASES = mult.tst
+
+all: $(TESTCASES)
+
+%.tst: %.c
+ $(CC) $(CFLAGS) $< -o $@
+
+check: $(TESTCASES)
+ @for case in $(TESTCASES); do \
+ echo $(SIM) $(SIM_FLAGS) ./$$case;\
+ $(SIM) $(SIM_FLAGS) ./$$case; \
+ done
+
+clean:
+ $(RM) -rf $(TESTCASES)
diff --git a/tests/tcg/mips/mipsr5900/mult.c b/tests/tcg/mips/mipsr5900/mult.c
new file mode 100644
index 0000000..2c0c16d
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/mult.c
@@ -0,0 +1,47 @@
+/*
+ * Test R5900-specific three-operand MULT.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+static int64_t mult(int32_t rs, int32_t rt)
+{
+ int32_t rd, lo, hi;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mult %0, %3, %4\n"
+ " mflo %1\n"
+ " mfhi %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert((int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static void verify_mult_negations(int32_t rs, int32_t rt, int64_t expected)
+{
+ assert(mult(rs, rt) == expected);
+ assert(mult(-rs, rt) == -expected);
+ assert(mult(rs, -rt) == -expected);
+ assert(mult(-rs, -rt) == expected);
+}
+
+int main()
+{
+ verify_mult_negations(17, 19, 323);
+ verify_mult_negations(77773, 99991, 7776600043);
+ verify_mult_negations(12207031, 305175781, 3725290219116211);
+
+ assert(mult(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
+ assert(mult(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(mult(-0x80000000, -0x80000000) == 0x4000000000000000);
+
+ return 0;
+}
--
2.7.4
- [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, (continued)
- [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/22