[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 17/28] pci-testdev: add optional memory bar
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL 17/28] pci-testdev: add optional memory bar |
Date: |
Tue, 23 Oct 2018 19:41:32 -0400 |
From: Gerd Hoffmann <address@hidden>
Add memory bar to pci-testdev. Size is configurable using the membar
property. Setting the size to zero (default) turns it off. Can be used
to check whether guests handle large pci bars correctly.
Reviewed-by: Marc-André Lureau <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Tested-by: Laszlo Ersek <address@hidden>
Signed-off-by: Gerd Hoffmann <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
docs/specs/pci-testdev.txt | 15 ++++++++++-----
hw/misc/pci-testdev.c | 19 +++++++++++++++++++
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/docs/specs/pci-testdev.txt b/docs/specs/pci-testdev.txt
index 128ae222ef..4280a1e73c 100644
--- a/docs/specs/pci-testdev.txt
+++ b/docs/specs/pci-testdev.txt
@@ -1,11 +1,11 @@
pci-test is a device used for testing low level IO
-device implements up to two BARs: BAR0 and BAR1.
-Each BAR can be memory or IO. Guests must detect
-BAR type and act accordingly.
+device implements up to three BARs: BAR0, BAR1 and BAR2.
+Each of BAR 0+1 can be memory or IO. Guests must detect
+BAR types and act accordingly.
-Each BAR size is up to 4K bytes.
-Each BAR starts with the following header:
+BAR 0+1 size is up to 4K bytes each.
+BAR 0+1 starts with the following header:
typedef struct PCITestDevHdr {
uint8_t test; <- write-only, starts a given test number
@@ -24,3 +24,8 @@ All registers are little endian.
device is expected to always implement tests 0 to N on each BAR, and to add new
tests with higher numbers. In this way a guest can scan test numbers until it
detects an access type that it does not support on this BAR, then stop.
+
+BAR2 is a 64bit memory bar, without backing storage. It is disabled
+by default and can be enabled using the membar=<size> property. This
+can be used to test whether guests handle pci bars of a specific
+(possibly quite large) size correctly.
diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c
index 32041f535f..a811b2ce20 100644
--- a/hw/misc/pci-testdev.c
+++ b/hw/misc/pci-testdev.c
@@ -85,6 +85,9 @@ typedef struct PCITestDevState {
MemoryRegion portio;
IOTest *tests;
int current;
+
+ size_t membar_size;
+ MemoryRegion membar;
} PCITestDevState;
#define TYPE_PCI_TEST_DEV "pci-testdev"
@@ -253,6 +256,16 @@ static void pci_testdev_realize(PCIDevice *pci_dev, Error
**errp)
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio);
+ if (d->membar_size) {
+ memory_region_init(&d->membar, OBJECT(d), "pci-testdev-membar",
+ d->membar_size);
+ pci_register_bar(pci_dev, 2,
+ PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_PREFETCH |
+ PCI_BASE_ADDRESS_MEM_TYPE_64,
+ &d->membar);
+ }
+
d->current = -1;
d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests);
for (i = 0; i < IOTEST_MAX; ++i) {
@@ -305,6 +318,11 @@ static void qdev_pci_testdev_reset(DeviceState *dev)
pci_testdev_reset(d);
}
+static Property pci_testdev_properties[] = {
+ DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_testdev_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -319,6 +337,7 @@ static void pci_testdev_class_init(ObjectClass *klass, void
*data)
dc->desc = "PCI Test Device";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->reset = qdev_pci_testdev_reset;
+ dc->props = pci_testdev_properties;
}
static const TypeInfo pci_testdev_info = {
--
MST
- [Qemu-devel] [PULL 00/28] pci, pc, virtio: fixes, features, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 04/28] intel_iommu: move ce fetching out when sync shadow, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 01/28] virtio-blk: fix comment for virtio_blk_rw_complete, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 05/28] intel_iommu: handle invalid ce for shadow sync, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 02/28] intel_iommu: introduce vtd_reset_caches(), Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 07/28] x86_iommu: move the kernel-irqchip check in common code, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 09/28] x86_iommu/amd: remove V=1 check from amdvi_validate_dte(), Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 16/28] MAINTAINERS: list "tests/acpi-test-data" files in ACPI/SMBIOS section, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 06/28] vhost-user-blk: start vhost when guest kicks, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 17/28] pci-testdev: add optional memory bar,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL 10/28] x86_iommu/amd: make the address space naming consistent with intel-iommu, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 24/28] pci_bridge: fix typo in comment, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 25/28] i440fx: use ARRAY_SIZE for pam_regions, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 08/28] x86_iommu: move vtd_generate_msi_message in common file, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 11/28] x86_iommu/amd: Prepare for interrupt remap support, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 19/28] hw/pci-host/x86: extend the 64-bit PCI hole relative to the fw-assigned base, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 03/28] intel_iommu: better handling of dmar state switch, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 20/28] tests/bios-tables-test: add 64-bit PCI MMIO aperture round-up test on Q35, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 13/28] i386: acpi: add IVHD device entry for IOAPIC, Michael S. Tsirkin, 2018/10/23
- [Qemu-devel] [PULL 15/28] x86_iommu/amd: Enable Guest virtual APIC support, Michael S. Tsirkin, 2018/10/23