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[Qemu-devel] [PATCH 11/11] disas/mips: Disassemble R5900 DIV[U]1, M{F, T
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH 11/11] disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1 |
Date: |
Thu, 25 Oct 2018 19:34:59 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Disassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1,
MTHI1, MULT1 and MULTU1.
Signed-off-by: Fredrik Noring <address@hidden>
---
disas/mips.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 9f01fda8bd..eddfb59325 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2323,6 +2323,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0,
I1 },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0,
I1 },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0,
I1 },
+{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s | RD_t | WR_HILO, 0, EE },
+{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_s | RD_t | WR_HILO, 0, EE },
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,
I1 },
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0,
I1 },
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,
SB1 },
@@ -2331,6 +2333,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0,
I1 },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0,
I1 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0,
I1 },
+{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s | RD_t | WR_HILO, 0, EE },
+{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_s | WR_HILO , 0, EE },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0,
I3 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0,
I3 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0,
I3 }, /* addiu */
@@ -2594,8 +2598,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0,
N5 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0,
I1 },
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0,
D32 },
+{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d | RD_HI, 0, EE},
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0,
I1 },
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0,
D32 },
+{"mflo1", "d", 0x70000012, 0xffff07ff, WR_d | RD_LO, 0, EE},
{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0,
SMT },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0,
MX|SB1 },
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0,
N54 },
@@ -2661,8 +2667,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0,
N5 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0,
I1 },
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0,
D32 },
+{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s | WR_HI, 0, EE },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0,
I1 },
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0,
D32 },
+{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s | WR_LO, 0, EE },
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0,
SMT },
{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,
MT32 },
{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,
MT32 },
@@ -2728,10 +2736,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,
I1 },
{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0,
D33 },
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,
0, G1 },
+{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M,
0, EE },
+{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO |
IS_M, 0, EE },
{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0,
SMT },
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,
I1 },
{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0,
D33 },
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M,
0, G1 },
+{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M,
0, EE },
+{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO |
IS_M, 0, EE },
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,
N5 },
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0,
I1 }, /* sub 0 */
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0,
I1 }, /* subu 0 */
--
2.18.1
- [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace, (continued)
- [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 02/11] target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 04/11] target/mips: Support R5900 three-operand MADD1 and MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 05/11] tests/tcg/mips: Test R5900 three-operand MADD, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 06/11] tests/tcg/mips: Test R5900 three-operand MADD1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 07/11] tests/tcg/mips: Test R5900 three-operand MADDU, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 08/11] tests/tcg/mips: Test R5900 three-operand MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 09/11] disas/mips: Increase 'member of ISAs' flag holder size, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 10/11] disas/mips: Define R5900 disassembly constants, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 11/11] disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1,
Fredrik Noring <=