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[Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLW
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases |
Date: |
Mon, 29 Oct 2018 16:19:52 +0100 |
From: Aleksandar Markovic <address@hidden>
Coverity found two fallthroughs that miss break statement. Fix them.
Revieved-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 51a5488..3bdefc0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -21321,6 +21321,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
check_eva(ctx);
check_cp0_enabled(ctx);
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
@@ -21339,6 +21340,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
check_eva(ctx);
check_cp0_enabled(ctx);
gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
--
2.7.4
- [Qemu-devel] [PULL 00/27] MIPS queue for October 2018, part 4, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 02/27] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 03/27] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 08/27] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 12/27] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 01/27] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 09/27] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 07/27] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 05/27] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 06/27] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 25/27] linux-user: Read and set FP ABI value from MIPS abiflags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 16/27] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 11/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/29