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[Qemu-devel] [PULL 1/7] i386: correct cpu_x86_cpuid(0xd)
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 1/7] i386: correct cpu_x86_cpuid(0xd) |
Date: |
Tue, 30 Oct 2018 21:45:44 -0300 |
From: Sebastian Andrzej Siewior <address@hidden>
Intel SDM says for CPUID function 0DH, sub-function 0:
| • ECX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components supported by this
| processor.
| • EBX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components corresponding to bits
| currently set in XCR0.
Signed-off-by: Sebastian Andrzej Siewior <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1469a1be01..fe7c963e5e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4178,7 +4178,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
*eax = env->features[FEAT_XSAVE_COMP_LO];
*edx = env->features[FEAT_XSAVE_COMP_HI];
- *ebx = *ecx;
+ *ebx = xsave_area_size(env->xcr0);
} else if (count == 1) {
*eax = env->features[FEAT_XSAVE];
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL 0/7] x86 queue, 2018-10-30, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 1/7] i386: correct cpu_x86_cpuid(0xd),
Eduardo Habkost <=
- [Qemu-devel] [PULL 5/7] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 7/7] i386: Add PKU on Skylake-Server CPU model, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 2/7] target/i386: Remove #ifdeffed-out icebp debugging hack, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 3/7] kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 6/7] i386: Add new model of Cascadelake-Server, Eduardo Habkost, 2018/10/30
- [Qemu-devel] [PULL 4/7] x86: Data structure changes to support MSR based features, Eduardo Habkost, 2018/10/30
- Re: [Qemu-devel] [PULL 0/7] x86 queue, 2018-10-30, Eduardo Habkost, 2018/10/31