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[Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers |
Date: |
Fri, 1 Feb 2019 16:06:24 +0000 |
The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
include/hw/arm/armsse.h | 1 +
hw/arm/armsse.c | 39 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 9855ec5f269..9d830057d5c 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -150,6 +150,7 @@ typedef struct ARMSSE {
UnimplementedDeviceState mhu[2];
UnimplementedDeviceState ppu[NUM_PPUS];
+ UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
/*
* 'container' holds all devices seen by all CPUs.
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 280ba5c78be..41e4a781e11 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -32,6 +32,7 @@ struct ARMSSEInfo {
SysConfigFormat sys_config_format;
bool has_mhus;
bool has_ppus;
+ bool has_cachectrl;
};
static const ARMSSEInfo armsse_variants[] = {
@@ -43,6 +44,7 @@ static const ARMSSEInfo armsse_variants[] = {
.sys_config_format = IoTKitFormat,
.has_mhus = false,
.has_ppus = false,
+ .has_cachectrl = false,
},
};
@@ -290,6 +292,16 @@ static void armsse_init(Object *obj)
g_free(name);
}
}
+ if (info->has_cachectrl) {
+ for (i = 0; i < info->num_cpus; i++) {
+ char *name = g_strdup_printf("cachectrl%d", i);
+
+ sysbus_init_child_obj(obj, name, &s->cachectrl[i],
+ sizeof(s->cachectrl[i]),
+ TYPE_UNIMPLEMENTED_DEVICE);
+ g_free(name);
+ }
+ }
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate,
sizeof(s->nmi_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
@@ -795,7 +807,32 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
armsse_get_common_irq_in(s, 10));
- /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */
+ /*
+ * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
+ * private per-CPU region (all these devices are SSE-200 only):
+ * 0x50010000: L1 icache control registers
+ * 0x50011000: CPUSECCTRL (CPU local security control registers)
+ * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
+ */
+ if (info->has_cachectrl) {
+ for (i = 0; i < info->num_cpus; i++) {
+ char *name = g_strdup_printf("cachectrl%d", i);
+ MemoryRegion *mr;
+
+ qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
+ g_free(name);
+ qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
+ object_property_set_bool(OBJECT(&s->cachectrl[i]), true,
+ "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
+ memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
+ }
+ }
/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
/* Devices behind APB PPC1:
--
2.20.1
- [Qemu-devel] [PULL 00/47] target-arm queue, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers,
Peter Maydell <=
- [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 42/47] linux-user: Initialize aarch64 pac keys, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 31/47] target/arm/translate-a64: Don't underdecode SDOT and UDOT, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 27/47] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple, Peter Maydell, 2019/02/01