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Re: [Qemu-devel] SeaBIOS regression
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From: |
Thomas Huth |
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Subject: |
Re: [Qemu-devel] SeaBIOS regression |
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Date: |
Thu, 7 Feb 2019 09:15:11 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 2019-02-06 18:29, John Snow wrote:
>
>
> On 2/5/19 4:47 AM, Thomas Huth wrote:
>> On 2019-02-05 10:42, Gerd Hoffmann wrote:
>>> On Tue, Feb 05, 2019 at 10:31:24AM +0100, Thomas Huth wrote:
>>>> On 2019-02-05 08:52, Gerd Hoffmann wrote:
>>>>> On Mon, Feb 04, 2019 at 04:10:37PM +0100, Thomas Huth wrote:
>>>>>>
>>>>>> Hi Gerd,
>>>>>>
>>>>>> I noticed that certain FreeDOS images are not working correctly anymore
>>>>>> with the current version of QEMU, for example
>>>>>> http://www.qemu-advent-calendar.org/2016/download/day10.tar.xz ... It
>>>>>> aborts with:
>>>>>>
>>>>>> Error reading from drive C: DOS area: write-protection violation
>>>>>> attempted
>>>>>>
>>>>>> I've bisected the issue, and it has apparently been introduced with:
>>>>>>
>>>>>> cd1bfd5ef336166b275a09dc9842542bf5e63ae3
>>>>>> seabios: update bios and vgabios binaries
>>>>>>
>>>>>> Any idea what might be going wrong here?
>>>>>
>>>>> Hmm, no. bisect seabios?
>>>>
>>>> I haven't bisected yet, but it seems to be related to CONFIG_ATA_DMA=y
>>>> in our roms/config.seabios-128k config file. When I switch that to "n",
>>>> then the old FreeDOS disks are working again...
>>>
>>> Hmm, guess I should turn that off again on the next update (there will
>>> be a seabios 1.12.1 release before qemu 4.0).
>>
>> Ah, right, I just noticed that this has just been enabled in QEMU for
>> the 3.0 release, where the problem occurred for the first time. So this
>> switch is likely the culprit, not a change in SeaBIOS. I'd also vote to
>> revert commit eda553a442e94d now.
>>
>> Thomas
>>
>
> If you enable the tracing in hw/ide/core, does it say anything that
> looks interesting? I'm wondering if there's some deficiency there.
At the end of the log, I can see:
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x01;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x84;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_write IDE PIO wr @ 0x1f7 (Command); val 0xc8;
ide_exec_cmd IDE exec cmd: bus 0x55eb8c5c0620; state 0x55eb8c5c0698; cmd 0xc8
ide_dma_cb IDEState 0x55eb8c5c0698; sector_num=132 n=1 cmd=DMA READ
ide_cancel_dma_sync_remaining draining all remaining requests
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0e;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0a;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xa0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x08;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x01;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x84;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_write IDE PIO wr @ 0x1f7 (Command); val 0xc8;
ide_exec_cmd IDE exec cmd: bus 0x55eb8c5c0620; state 0x55eb8c5c0698; cmd 0xc8
ide_dma_cb IDEState 0x55eb8c5c0698; sector_num=132 n=1 cmd=DMA READ
ide_cancel_dma_sync_remaining draining all remaining requests
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0e;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0a;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xa0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x08;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x01;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x84;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_write IDE PIO wr @ 0x1f7 (Command); val 0xc8;
ide_exec_cmd IDE exec cmd: bus 0x55eb8c5c0620; state 0x55eb8c5c0698; cmd 0xc8
ide_dma_cb IDEState 0x55eb8c5c0698; sector_num=132 n=1 cmd=DMA READ
ide_cancel_dma_sync_remaining draining all remaining requests
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0e;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0a;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xa0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x08;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x01;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x84;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_write IDE PIO wr @ 0x1f7 (Command); val 0xc8;
ide_exec_cmd IDE exec cmd: bus 0x55eb8c5c0620; state 0x55eb8c5c0698; cmd 0xc8
ide_dma_cb IDEState 0x55eb8c5c0698; sector_num=132 n=1 cmd=DMA READ
ide_cancel_dma_sync_remaining draining all remaining requests
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0e;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0a;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xa0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x08;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f2 (Sector Count); val 0x01;
ide_ioport_write IDE PIO wr @ 0x1f3 (Sector Number); val 0x84;
ide_ioport_write IDE PIO wr @ 0x1f4 (Cylinder Low); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f5 (Cylinder High); val 0x00;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xe0;
ide_ioport_write IDE PIO wr @ 0x1f7 (Command); val 0xc8;
ide_exec_cmd IDE exec cmd: bus 0x55eb8c5c0620; state 0x55eb8c5c0698; cmd 0xc8
ide_dma_cb IDEState 0x55eb8c5c0698; sector_num=132 n=1 cmd=DMA READ
ide_cancel_dma_sync_remaining draining all remaining requests
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0e;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x0a;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_ioport_write IDE PIO wr @ 0x1f6 (Device/Head); val 0xa0;
ide_ioport_read IDE PIO rd @ 0x1f7 (Status); val 0x50;
ide_cmd_write IDE PIO wr @ 0x3f6 (Device Control); val 0x08;
Looks like command 0xc8 (READDMA) goes wrong for some reason?
Anyway, looking at commit eda553a442e94dc16d424849b65c6cb7f1
it seems like there is a known problem in SeaBIOS with
CONFIG_ATA_DMA=y with real hardware - so maybe we just hit
the same problem here, too? That would mean that the bug
is in SeaBIOS and not in QEMU, thus we should simply disable
that config switch again.
Thomas