Re: [Qemu-devel] [PULL 00/27] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PULL 00/27] target-arm queue
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
79f823dd50 gdbstub: Send a reply to the vKill packet.
54055c690e target/arm: Add missing clear_tail calls
256e4557f2 target/arm: Use vector operations for saturation
dac47f6b64 target/arm: Split out FPSCR.QC to a vector field
dffbd3cd1b target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
003ad968a8 target/arm: Split out flags setting from vfp compares
8e2cdb45d1 target/arm: Fix arm_cpu_dump_state vs FPSCR
c6859c1a84 target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
6a0a150b2d target/arm: Remove neon min/max helpers
ced3d5e3d9 target/arm: Use tcg integer min/max primitives for neon
0f1a572c84 target/arm: Use vector minmax expanders for aarch32
66e0205bc3 target/arm: Use vector minmax expanders for aarch64
2ce0e8773f target/arm: Rely on optimization within tcg_gen_gvec_or
6bd399ef3d hw/arm/armsse: Fix miswiring of expansion IRQs
ee3a0f2e15 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
f2bd89cfd3 MAINTAINERS: Remove Peter Crosthwaite from various entries
0d2f803513 arm: Allow system registers for KVM guests to be changed by QEMU code
8d7c1af9f3 linux-user/elfload: enable HWCAP_CPUID for AArch64
87d553b62c target/arm: expose remaining CPUID registers as RAZ
2296abadfb target/arm: expose MPIDR_EL1 to userspace
682347fb9e target/arm: expose CPUID registers to userspace
61e1e876ae target/arm: relax permission checks for HWCAP_CPUID registers
a03d01166b target/arm: Restructure disas_fp_int_conv
49c75fb14d target/arm: Force result size into dp after operation
b311548ce5 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
6d9154655f target/arm: Implement HACR_EL2
b6a2f6e7d0 target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

=== OUTPUT BEGIN ===
1/27 Checking commit b6a2f6e7d009 (target/arm: Fix CRn to be 14 for 
PMEVTYPER/PMEVCNTR)
2/27 Checking commit 6d9154655f8f (target/arm: Implement HACR_EL2)
3/27 Checking commit b311548ce515 (target/arm: Fix int128_make128 lo, hi order 
in paired_cmpxchg64_be)
4/27 Checking commit 49c75fb14d08 (target/arm: Force result size into dp after 
operation)
5/27 Checking commit a03d01166b02 (target/arm: Restructure disas_fp_int_conv)
6/27 Checking commit 61e1e876ae47 (target/arm: relax permission checks for 
HWCAP_CPUID registers)
7/27 Checking commit 682347fb9e39 (target/arm: expose CPUID registers to 
userspace)
8/27 Checking commit 2296abadfb9a (target/arm: expose MPIDR_EL1 to userspace)
9/27 Checking commit 87d553b62c30 (target/arm: expose remaining CPUID registers 
as RAZ)
10/27 Checking commit 8d7c1af9f3f9 (linux-user/elfload: enable HWCAP_CPUID for 
AArch64)
11/27 Checking commit 0d2f8035130d (arm: Allow system registers for KVM guests 
to be changed by QEMU code)
12/27 Checking commit f2bd89cfd3fb (MAINTAINERS: Remove Peter Crosthwaite from 
various entries)
13/27 Checking commit ee3a0f2e1566 (hw/intc/armv7m_nvic: Allow byte accesses to 
SHPR1)
14/27 Checking commit 6bd399ef3d57 (hw/arm/armsse: Fix miswiring of expansion 
IRQs)
15/27 Checking commit 2ce0e8773f22 (target/arm: Rely on optimization within 
tcg_gen_gvec_or)
16/27 Checking commit 66e0205bc37e (target/arm: Use vector minmax expanders for 
aarch64)
17/27 Checking commit 0f1a572c8401 (target/arm: Use vector minmax expanders for 
aarch32)
18/27 Checking commit ced3d5e3d9eb (target/arm: Use tcg integer min/max 
primitives for neon)
19/27 Checking commit 6a0a150b2da5 (target/arm: Remove neon min/max helpers)
20/27 Checking commit c6859c1a849d (target/arm: Fix vfp_gdb_get/set_reg vs 
FPSCR)
ERROR: trailing statements should be on next line
#25: FILE: target/arm/helper.c:84:
+    case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;

ERROR: trailing statements should be on next line
#34: FILE: target/arm/helper.c:110:
+    case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;

total: 2 errors, 0 warnings, 16 lines checked

Patch 20/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

21/27 Checking commit 8e2cdb45d186 (target/arm: Fix arm_cpu_dump_state vs FPSCR)
22/27 Checking commit 003ad968a808 (target/arm: Split out flags setting from 
vfp compares)
23/27 Checking commit dffbd3cd1b4d (target/arm: Fix set of bits kept in 
xregs[ARM_VFP_FPSCR])
24/27 Checking commit dac47f6b645f (target/arm: Split out FPSCR.QC to a vector 
field)
25/27 Checking commit 256e4557f2e8 (target/arm: Use vector operations for 
saturation)
ERROR: spaces required around that '*' (ctx:WxV)
#360: FILE: target/arm/vec_helper.c:774:
+    TYPEN *d = vd, *n = vn; TYPEM *m = vm;                                 \
                                   ^

total: 1 errors, 0 warnings, 438 lines checked

Patch 25/27 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

26/27 Checking commit 54055c690e1f (target/arm: Add missing clear_tail calls)
27/27 Checking commit 79f823dd5021 (gdbstub: Send a reply to the vKill packet.)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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