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Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8b
From: |
Yoshinori Sato |
Subject: |
Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers |
Date: |
Sun, 14 Apr 2019 23:55:32 +0900 |
User-agent: |
Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (Gojō) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) |
On Thu, 11 Apr 2019 19:09:38 +0900,
Philippe Mathieu-Daudé wrote:
>
> Hi Yoshinori,
>
> Note about the patch subject:
> - typo in regiserfields (missing 't') -> registerfields
> - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros"
OK.
> On 4/1/19 4:03 PM, Yoshinori Sato wrote:
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
> >
> > Signed-off-by: Yoshinori Sato <address@hidden>
> > ---
> > include/hw/registerfields.h | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> > index 2659a58737..f6bf911990 100644
> > --- a/include/hw/registerfields.h
> > +++ b/include/hw/registerfields.h
> > @@ -22,6 +22,14 @@
> > enum { A_ ## reg = (addr) }; \
> > enum { R_ ## reg = (addr) / 4 };
> >
> > +#define REG8(reg, addr) \
> > + enum { A_ ## reg = (addr) }; \
> > + enum { R_ ## reg = (addr) };
> > +
> > +#define REG16(reg, addr) \
> > + enum { A_ ## reg = (addr) }; \
> > + enum { R_ ## reg = (addr) / 2 };
> > +
> > /* Define SHIFT, LENGTH and MASK constants for a field within a register */
> >
> > /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and
> > R_FOO_BAR_LENGTH
> > @@ -40,6 +48,8 @@
> > #define FIELD_EX64(storage, reg, field) \
> > extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> > R_ ## reg ## _ ## field ## _LENGTH)
> > +#define FIELD_EX8 FIELD_EX32
> > +#define FIELD_EX16 FIELD_EX32
> >
> > /* Extract a field from an array of registers */
> > #define ARRAY_FIELD_EX32(regs, reg, field) \
>
> For completeness, what about adding FIELD_DP8() and FIELD_DP16()?
I did not add it because I did not use it.
Certainly it is strange that there is no these, so I will add it.
As the registerfields support is incomplete, we will fix it together.
> Regards,
>
> Phil.
>
--
Yosinori Sato
- [Qemu-devel] [PATCH RFC v6 00/12] Add RX archtecture support, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 05/12] target/rx: Miscellaneous files, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 10/12] Add rx-softmmu, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 03/12] target/rx: CPU definition, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 09/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 06/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 04/12] target/rx: RX disassembler, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 08/12] hw/char: RX62N serical communication interface (SCI), Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 11/12] MAINTAINERS: Add RX, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 07/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/04/01
- [Qemu-devel] [PATCH RFC v6 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/04/01
- Re: [Qemu-devel] [PATCH RFC v6 00/12] Add RX archtecture support, no-reply, 2019/04/01
- Re: [Qemu-devel] [PATCH RFC v6 00/12] Add RX archtecture support, Philippe Mathieu-Daudé, 2019/04/11