Re: [Qemu-devel] [Qemu-ppc] [PATCH v7 5/6] ppc: spapr: Enable FWNMI capability

[Aravinda Prasad]

On Tuesday 26 March 2019 05:03 AM, David Gibson wrote:
> On Mon, Mar 25, 2019 at 02:27:45PM +0530, Aravinda Prasad wrote:
>>
>>
>> On Monday 25 March 2019 12:02 PM, David Gibson wrote:
>>> On Fri, Mar 22, 2019 at 12:04:16PM +0530, Aravinda Prasad wrote:
>>>> Enable the KVM capability KVM_CAP_PPC_FWNMI so that
>>>> the KVM causes guest exit with NMI as exit reason
>>>> when it encounters a machine check exception on the
>>>> address belonging to a guest. Without this capability
>>>> enabled, KVM redirects machine check exceptions to
>>>> guest's 0x200 vector.
>>>>
>>>> Signed-off-by: Aravinda Prasad <address@hidden>
>>>> ---
>>>>  hw/ppc/spapr_rtas.c  |   15 +++++++++++++++
>>>>  target/ppc/kvm.c     |   14 ++++++++++++++
>>>>  target/ppc/kvm_ppc.h |    6 ++++++
>>>>  3 files changed, 35 insertions(+)
>>>>
>>>> diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
>>>> index fb594a4..939f428 100644
>>>> --- a/hw/ppc/spapr_rtas.c
>>>> +++ b/hw/ppc/spapr_rtas.c
>>>> @@ -49,6 +49,7 @@
>>>>  #include "hw/ppc/fdt.h"
>>>>  #include "target/ppc/mmu-hash64.h"
>>>>  #include "target/ppc/mmu-book3s-v3.h"
>>>> +#include "kvm_ppc.h"
>>>>  
>>>>  static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState 
>>>> *spapr,
>>>>                                     uint32_t token, uint32_t nargs,
>>>> @@ -354,6 +355,20 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
>>>>                                    target_ulong args,
>>>>                                    uint32_t nret, target_ulong rets)
>>>>  {
>>>> +    int ret;
>>>> +
>>>> +    ret = kvmppc_fwnmi_enable(cpu);
>>>> +
>>>> +    if (ret == 1) {
>>>> +        rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
>>>
>>> Urgh, we're here making a guest visible different to the environment
>>> depending on a host (KVM) capability.  What happens if you start a
>>> guest and it registers fwnmi support, then migrate it to a host that
>>> lacks the necessary KVM support?
>>
>> I just checked how such scenarios are handled for other KVM
>> capabilities. Should I need to add an Spapr cap for this?
> 
> Yes, I think that's what we'll need to do.

I was looking into SPAPR Cap, and I am not sure that the following code
will help in handling the migration. I need some help here.

diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index edc5ed0..ef96192 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -473,6 +473,15 @@ static void cap_ccf_assist_apply(SpaprMachineState
*spapr, uint8_t val,
     }
 }

+static void cap_machine_check_apply(SpaprMachineState *spapr, uint8_t val,
+                                    Error **errp)
+{
+    if (kvm_enabled()) {
+        if (kvmppc_fwnmi_enable(cpu)) {
+            error_setg(errp, "Unable to enable fwnmi capability");
+    }
+}
+
 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
     [SPAPR_CAP_HTM] = {
         .name = "htm",
@@ -571,6 +580,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
         .type = "bool",
         .apply = cap_ccf_assist_apply,
     },
+    [SPAPR_CAP_MACHINE_CHECK] = {
+        .name = "machine-check",
+        .description = "Handle machine check exceptions",
+        .index = SPAPR_CAP_MACHINE_CHECK,
+        .get = spapr_cap_get_bool,
+        .set = spapr_cap_set_bool,
+        .type = "bool",
+        .apply = cap_machine_check_apply,
+    },
 };

 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
@@ -706,6 +724,7 @@ SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
 SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
 SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
 SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
+SPAPR_CAP_MIG_STATE(mce, SPAPR_CAP_MACHINE_CHECK);

 void spapr_caps_init(SpaprMachineState *spapr)
 {


Or is it that just adding SPAPR_CAP_MIG_STATE(mce,
SPAPR_CAP_MACHINE_CHECK); is enough as it is checking or cap values?

> 

-- 
Regards,
Aravinda