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[Qemu-devel] [PATCH v7 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA ins
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v7 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions |
Date: |
Wed, 17 Apr 2019 17:33:25 +0200 |
>From 55e222d8139e3dd034069fb512b83fd2541ec067 Mon Sep 17 00:00:00 2001
From: Mateja Marjanovic <address@hidden>
Date: Wed, 17 Apr 2019 14:50:55 +0200
Subject: [PATCH v7 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/translate.c | 28 ++++++++++------------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4c7b076..656153a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28961,20 +28961,6 @@ static inline void gen_ilvr_w(CPUMIPSState *env,
uint32_t wd,
}
/*
- * [MSA] ILVR.D wd, ws, wt
- *
- * Vector Interleave Right (doubleword data elements)
- *
- */
-static inline void gen_ilvr_d(CPUMIPSState *env, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
- tcg_gen_mov_i64(msa_wr_d[wd * 2], msa_wr_d[wt * 2]);
-}
-
-
-/*
* [MSA] ILVL.H wd, ws, wt
*
* Vector Interleave Left (halfword data elements)
@@ -29197,10 +29183,16 @@ static inline void gen_ilvev_w(CPUMIPSState *env,
uint32_t wd,
/*
* [MSA] ILVEV.D wd, ws, wt
*
- * Vector Interleave Even (Doubleword data elements)
+ * Vector Interleave Even (doubleword data elements)
+ *
+ * [MSA] ILVR.D wd, ws, wt
+ *
+ * Vector Interleave Right (doubleword data elements)
+ *
+ * These two instructions are functionally equivalent.
*
*/
-static inline void gen_ilvev_d(CPUMIPSState *env, uint32_t wd,
+static inline void gen_ilvev_ilvr_d(CPUMIPSState *env, uint32_t wd,
uint32_t ws, uint32_t wt)
{
tcg_gen_mov_i64(msa_wr_d[wd * 2 + 1], msa_wr_d[ws * 2]);
@@ -29374,7 +29366,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext
*ctx)
gen_ilvr_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvr_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
@@ -29404,7 +29396,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext
*ctx)
gen_ilvev_w(env, wd, ws, wt);
break;
case DF_DOUBLE:
- gen_ilvev_d(env, wd, ws, wt);
+ gen_ilvev_ilvr_d(env, wd, ws, wt);
break;
default:
assert(0);
--
2.7.4
- [Qemu-devel] [PATCH v7 0/6] target/mips: Optimize MSA interleave instructions, Mateja Marjanovic, 2019/04/17
- [Qemu-devel] [PATCH v7 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/17
- [Qemu-devel] [PATCH v7 1/6] target/mips: Optimize ILVOD.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/17
- [Qemu-devel] [PATCH v7 3/6] target/mips: Optimize ILVL.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/17
- [Qemu-devel] [PATCH v7 6/6] target/mips: Merge implementation of ILVOD.D and ILVL.D, Mateja Marjanovic, 2019/04/17
- [Qemu-devel] [PATCH v7 4/6] target/mips: Optimize ILVR.<B|H|W|D> MSA instructions,
Mateja Marjanovic <=
- [Qemu-devel] [PATCH v7 2/6] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions, Mateja Marjanovic, 2019/04/17
- Re: [Qemu-devel] [PATCH v7 0/6] target/mips: Optimize MSA interleave instructions, Aleksandar Markovic, 2019/04/17