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[Qemu-devel] [Bug 1825311] Re: mips_cpu_handle_mmu_fault renders all acc
From: |
Jakub Jermar |
Subject: |
[Qemu-devel] [Bug 1825311] Re: mips_cpu_handle_mmu_fault renders all accessed pages executable |
Date: |
Tue, 23 Apr 2019 14:48:44 -0000 |
I am attaching a reproducer image and script.
Unpatched execution ends like this:
...
TAP TEST START
1..2
not ok 1 NonExecutable::ElfDataIsNotExecutable
# Assertion failed
/home/jermar/Kernkonzept/software/l4/pkg/l4re-core/test/moe/test_nx.cc:103
# Expected: -(L4_EIPC_LO + l4_ipc_error(tag, l4_utcb())) >= 0
# Actual: -2003 (Receive timeout)
# There was no IPC error.
# Assertion failed
/home/jermar/Kernkonzept/software/l4/pkg/l4re-core/test/moe/test_nx.cc:125
# Expected equality of these values:
# pfa
# Which is: 360
# (l4_addr_t)execute_data
# Which is: 17633344
# The page fault occured at the expected location.
not ok 2 NonExecutable::StackIsNotExecutable
# Assertion failed
/home/jermar/Kernkonzept/software/l4/pkg/l4re-core/test/moe/test_nx.cc:103
# Expected: -(L4_EIPC_LO + l4_ipc_error(tag, l4_utcb())) >= 0
# Actual: -2003 (Receive timeout)
# There was no IPC error.
# Assertion failed
/home/jermar/Kernkonzept/software/l4/pkg/l4re-core/test/moe/test_nx.cc:144
# Expected equality of these values:
# pfa
# Which is: 4358144
# stack_func
# Which is: 4276000
# The page fault occured at the expected location.
TAP TEST FINISHED
With the proposed patch applied, the execution should end with something
like this:
...
TAP TEST START
1..2
ok 1 NonExecutable::ElfDataIsNotExecutable
ok 2 NonExecutable::StackIsNotExecutable
TAP TEST FINISHED
** Attachment added: "Image and script for reproducing this bug."
https://bugs.launchpad.net/qemu/+bug/1825311/+attachment/5258264/+files/reproducer.tar.xz
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https://bugs.launchpad.net/bugs/1825311
Title:
mips_cpu_handle_mmu_fault renders all accessed pages executable
Status in QEMU:
New
Bug description:
On MIPS, data accesses to pages mapped in the TLB result in
mips_cpu_handle_mmu_fault() marking the page unconditionally
executable, even if the TLB entry has the XI bit set. Later on, when
there is an attempt to execute this page, no exception is generated,
even though TLBXI is expected.
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