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[Qemu-devel] [PULL 4/4] Pass through cache information for TOPOEXT CPUs
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 4/4] Pass through cache information for TOPOEXT CPUs |
Date: |
Thu, 25 Apr 2019 15:13:42 -0300 |
From: Stanislav Lanci <address@hidden>
Signed-off-by: Stanislav Lanci <address@hidden>
Message-Id: <address@hidden>
[ehabkost: removed redundant comment line]
Signed-off-by: Eduardo Habkost <address@hidden>
---
target/i386/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d92b0f6fcc..722c5514d4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4591,6 +4591,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
case 0x8000001D:
*eax = 0;
+ if (cpu->cache_info_passthrough) {
+ host_cpuid(index, count, eax, ebx, ecx, edx);
+ break;
+ }
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL 0/4] x86 queue, 2019-04-25, Eduardo Habkost, 2019/04/25
- [Qemu-devel] [PULL 1/4] i386: Add new Hygon 'Dhyana' CPU model, Eduardo Habkost, 2019/04/25
- [Qemu-devel] [PULL 2/4] Categorize devices: IGD passthrough ISA bridge, Eduardo Habkost, 2019/04/25
- [Qemu-devel] [PULL 3/4] Categorize devices: iommu, Eduardo Habkost, 2019/04/25
- [Qemu-devel] [PULL 4/4] Pass through cache information for TOPOEXT CPUs,
Eduardo Habkost <=
- Re: [Qemu-devel] [PULL 0/4] x86 queue, 2019-04-25, Peter Maydell, 2019/04/27