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[Qemu-devel] [PULL 15/36] target/ppc: Style fixes for mem_helper.c
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 15/36] target/ppc: Style fixes for mem_helper.c |
Date: |
Fri, 26 Apr 2019 16:06:06 +1000 |
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
target/ppc/mem_helper.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 9c5a68579e..5b0f9ee50d 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -27,7 +27,7 @@
#include "internal.h"
#include "qemu/atomic128.h"
-//#define DEBUG_OP
+/* #define DEBUG_OP */
static inline bool needs_byteswap(const CPUPPCState *env)
{
@@ -103,10 +103,11 @@ void helper_lsw(CPUPPCState *env, target_ulong addr,
uint32_t nb, uint32_t reg)
do_lsw(env, addr, nb, reg, GETPC());
}
-/* PPC32 specification says we must generate an exception if
- * rA is in the range of registers to be loaded.
- * In an other hand, IBM says this is valid, but rA won't be loaded.
- * For now, I'll follow the spec...
+/*
+ * PPC32 specification says we must generate an exception if rA is in
+ * the range of registers to be loaded. In an other hand, IBM says
+ * this is valid, but rA won't be loaded. For now, I'll follow the
+ * spec...
*/
void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
uint32_t ra, uint32_t rb)
@@ -199,7 +200,8 @@ void helper_dcbzep(CPUPPCState *env, target_ulong addr,
uint32_t opcode)
void helper_icbi(CPUPPCState *env, target_ulong addr)
{
addr &= ~(env->dcache_line_size - 1);
- /* Invalidate one cache line :
+ /*
+ * Invalidate one cache line :
* PowerPC specification says this is to be treated like a load
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
@@ -346,17 +348,19 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env,
target_ulong addr,
#define LO_IDX 0
#endif
-/* We use msr_le to determine index ordering in a vector. However,
- byteswapping is not simply controlled by msr_le. We also need to take
- into account endianness of the target. This is done for the little-endian
- PPC64 user-mode target. */
+/*
+ * We use msr_le to determine index ordering in a vector. However,
+ * byteswapping is not simply controlled by msr_le. We also need to
+ * take into account endianness of the target. This is done for the
+ * little-endian PPC64 user-mode target.
+ */
#define LVE(name, access, swap, element) \
void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
target_ulong addr) \
{ \
size_t n_elems = ARRAY_SIZE(r->element); \
- int adjust = HI_IDX*(n_elems - 1); \
+ int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
if (msr_le) { \
@@ -476,12 +480,13 @@ VSX_STXVL(stxvll, 1)
void helper_tbegin(CPUPPCState *env)
{
- /* As a degenerate implementation, always fail tbegin. The reason
+ /*
+ * As a degenerate implementation, always fail tbegin. The reason
* given is "Nesting overflow". The "persistent" bit is set,
* providing a hint to the error handler to not retry. The TFIAR
* captures the address of the failure, which is this tbegin
- * instruction. Instruction execution will continue with the
- * next instruction in memory, which is precisely what we want.
+ * instruction. Instruction execution will continue with the next
+ * instruction in memory, which is precisely what we want.
*/
env->spr[SPR_TEXASR] =
--
2.20.1
- [Qemu-devel] [PULL 16/36] target/ppc: Style fixes for mfrom_table.inc.c & mfrom_table_gen.c, (continued)
- [Qemu-devel] [PULL 16/36] target/ppc: Style fixes for mfrom_table.inc.c & mfrom_table_gen.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 13/36] target/ppc: Style fixes for kvm_ppc.h and kvm.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 06/36] target/ppc: Style fixes for cpu.[ch], David Gibson, 2019/04/26
- [Qemu-devel] [PULL 10/36] target/ppc: Style fixes for excp_helper.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 08/36] target/ppc: Style fixes for fpu_helper.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 01/36] spapr: Support NVIDIA V100 GPU with NVLink2, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 14/36] target/ppc: Style fixes for machine.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 21/36] target/ppc: Style fixes for monitor.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 26/36] target/ppc: Style fixes for translate/vmx-impl.inc.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 23/36] target/ppc: Style fixes for translate.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 15/36] target/ppc: Style fixes for mem_helper.c,
David Gibson <=
- [Qemu-devel] [PULL 19/36] target/ppc: Style fixes for mmu-hash64.[ch], David Gibson, 2019/04/26
- [Qemu-devel] [PULL 24/36] target/ppc: Style fixes for translate/fp-impl.inc.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 29/36] spapr: Drop duplicate PCI swizzle code, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 20/36] target/ppc: Style fixes for mmu_helper.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 27/36] target/ppc: Style fixes for translate/spe-impl.inc.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 28/36] spapr_pci: Get rid of duplicate code for node name creation, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 22/36] target/ppc: Style fixes for translate_init.inc.c, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 34/36] ppc/hash64: Rework R and C bit updates, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 32/36] target/ppc: Don't check UPRT in radix mode when in HV real mode, David Gibson, 2019/04/26
- [Qemu-devel] [PULL 25/36] target/ppc: Style fixes for translate/vsx-impl.inc.c, David Gibson, 2019/04/26