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[Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shift
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64 |
Date: |
Fri, 26 Apr 2019 10:24:09 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index deacc63e3b..fbc70649dd 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1355,31 +1355,32 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,
TCGv_i64 arg1,
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
}
- } else {
- TCGv_i32 t0, t1;
-
- t0 = tcg_temp_new_i32();
- t1 = tcg_temp_new_i32();
- if (right) {
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
- if (arith) {
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
- } else {
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
- }
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
+ } else if (right) {
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_LOW(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
} else {
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
- /* Note: ret can be the same as arg1, so we use t1 */
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
+ TCGV_HIGH(arg1), 32 - c, c);
}
- tcg_temp_free_i32(t0);
- tcg_temp_free_i32(t1);
+ if (arith) {
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
+ } else {
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
+ }
+ } else {
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_HIGH(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
+ TCGV_HIGH(arg1), c, 32 - c);
+ tcg_temp_free_i32(t0);
+ }
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
}
}
--
2.17.1
- [Qemu-devel] [PULL 00/15] tcg patch queue, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64}, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64,
Richard Henderson <=
- [Qemu-devel] [PULL 04/15] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 05/15] tcg/i386: Support INDEX_op_extract2_{i32, i64}, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 02/15] tcg: Add INDEX_op_extract2_{i32,i64}, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 06/15] tcg/arm: Support INDEX_op_extract2_i32, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 07/15] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 09/15] tcg: Restart after TB code generation overflow, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 08/15] tcg: Hoist max_insns computation to tb_gen_code, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 11/15] tcg: Restart TB generation after constant pool overflow, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 10/15] tcg: Restart TB generation after relocation overflow, Richard Henderson, 2019/04/26
- [Qemu-devel] [PULL 12/15] tcg: Restart TB generation after out-of-line ldst overflow, Richard Henderson, 2019/04/26