[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-pro
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-profile |
Date: |
Mon, 29 Apr 2019 17:59:55 +0100 |
The only "system register" that M-profile floating point exposes
via the VMRS/VMRS instructions is FPSCR, and it does not have
the odd special case for rd==15. Add a check to ensure we only
expose FPSCR.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4ea4018e2b8..a9784535069 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3513,12 +3513,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
insn)
}
}
} else { /* !dp */
+ bool is_sysreg;
+
if ((insn & 0x6f) != 0x00)
return 1;
rn = VFP_SREG_N(insn);
+
+ is_sysreg = extract32(insn, 21, 1);
+
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ /*
+ * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
+ * Writes to R15 are UNPREDICTABLE; we choose to undef.
+ */
+ if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR))
{
+ return 1;
+ }
+ }
+
if (insn & ARM_CP_RW_BIT) {
/* vfp->arm */
- if (insn & (1 << 21)) {
+ if (is_sysreg) {
/* system register */
rn >>= 1;
@@ -3585,7 +3600,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
}
} else {
/* arm->vfp */
- if (insn & (1 << 21)) {
+ if (is_sysreg) {
rn >>= 1;
/* system register */
switch (rn) {
--
2.20.1
- [Qemu-devel] [PULL 00/42] target-arm queue, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 02/42] hw/ssi/xilinx_spips: Avoid variable length array, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 06/42] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 03/42] configure: Remove --source-path option, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 01/42] hw/arm/smmuv3: Remove SMMUNotifierNode, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-profile,
Peter Maydell <=
- [Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 17/42] target/arm: Allow for floating point in callee stack integrity check, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 13/42] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing M-profile floating point insns, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 08/42] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 24/42] target/arm: New function armv7m_nvic_set_pending_lazyfp(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 30/42] hw/dma: Compile the bcm2835_dma device as common object, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 32/42] hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string, Peter Maydell, 2019/04/29