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Re: [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_f
From: |
Max Filippov |
Subject: |
Re: [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_fill |
Date: |
Tue, 30 Apr 2019 10:32:14 -0700 |
On Tue, Apr 30, 2019 at 3:11 AM Peter Maydell <address@hidden> wrote:
>
> On Wed, 3 Apr 2019 at 05:00, Richard Henderson
> <address@hidden> wrote:
> >
> > Cc: Max Filippov <address@hidden>
> > Signed-off-by: Richard Henderson <address@hidden>
> > ---
> > target/xtensa/cpu.h | 5 +--
> > target/xtensa/cpu.c | 5 ++-
> > target/xtensa/helper.c | 74 +++++++++++++++++++++---------------------
> > 3 files changed, 42 insertions(+), 42 deletions(-)
>
> > -#ifdef CONFIG_USER_ONLY
> > -
> > -int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int
> > rw,
> > - int mmu_idx)
> > +bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> > + MMUAccessType access_type, int mmu_idx,
> > + bool probe, uintptr_t retaddr)
> > {
> > XtensaCPU *cpu = XTENSA_CPU(cs);
> > CPUXtensaState *env = &cpu->env;
> > + target_ulong vaddr = address;
> > + int ret;
> >
> > - qemu_log_mask(CPU_LOG_INT,
> > - "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size =
> > %d\n",
> > - __func__, rw, address, size);
> > - env->sregs[EXCVADDR] = address;
> > - env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE :
> > LOAD_PROHIBITED_CAUSE;
> > - cs->exception_index = EXC_USER;
> > - return 1;
>
> Previously we set exception_index to EXC_USER...
>
> > +#ifdef CONFIG_USER_ONLY
> > + ret = (access_type == MMU_DATA_STORE ?
> > + STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE);
> > +#else
> > + uint32_t paddr;
> > + uint32_t page_size;
> > + unsigned access;
> > +
> > + ret = xtensa_get_physical_addr(env, true, vaddr, access_type, mmu_idx,
> > + &paddr, &page_size, &access);
> > +
> > + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
> > + __func__, vaddr, access_type, mmu_idx, paddr, ret);
> > +
> > + if (ret == 0) {
> > + tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr &
> > TARGET_PAGE_MASK,
> > + access, mmu_idx, page_size);
> > + return true;
> > + }
> > + if (probe) {
> > + return false;
> > + }
> > +#endif
> > +
> > + cpu_restore_state(cs, retaddr, true);
> > + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
>
> ...but now we'll set it to whatever exception_cause_vaddr does,
> which is something more complicated based on the state of
> env->sregs[PS].
>
> We'll also end up setting env->sregs[PS] bits and env->pc, which
> the old code did not. (In particular since we set the PS_EXCM bit,
> the second time we take an exception won't we then end up
> setting exception_index to EXC_DOUBLE, not EXC_USER ?)
I guess it doesn't matter, because linux-user userspace never handles
exceptions. PS, PC and similar must be fixed up by the linux-user
exception handler. But I haven't tested it.
Richard, is there a branch with this series available somewhere?
--
Thanks.
-- Max
- [Qemu-devel] [PATCH 19/26] target/sparc: Convert to CPUClass::tlb_fill, (continued)
- [Qemu-devel] [PATCH 19/26] target/sparc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 20/26] target/tilegx: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 21/26] target/tricore: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 22/26] target/unicore32: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 23/26] target/xtensa: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
[Qemu-devel] [PATCH 24/26] tcg: Use CPUClass::tlb_fill in cputlb.c, Richard Henderson, 2019/04/02
[Qemu-devel] [PATCH 25/26] tcg: Remove CPUClass::handle_mmu_fault, Richard Henderson, 2019/04/02
[Qemu-devel] [PATCH 26/26] tcg: Use tlb_fill probe from tlb_vaddr_to_host, Richard Henderson, 2019/04/02