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[PATCH 09/35] target/i386: validate SSE prefixes directly in the decodin
From: |
Paolo Bonzini |
Subject: |
[PATCH 09/35] target/i386: validate SSE prefixes directly in the decoding table |
Date: |
Thu, 13 Oct 2022 23:46:25 +0200 |
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/decode-new.c.inc | 37 ++++++++++++++++++++++++++++++++
target/i386/tcg/decode-new.h | 1 +
2 files changed, 38 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index f0d7b24a07..ff3f45dc8c 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -110,6 +110,22 @@
#define avx2_256 .vex_special = X86_VEX_AVX2_256,
+#define P_00 1
+#define P_66 (1 << PREFIX_DATA)
+#define P_F3 (1 << PREFIX_REPZ)
+#define P_F2 (1 << PREFIX_REPNZ)
+
+#define p_00 .valid_prefix = P_00,
+#define p_66 .valid_prefix = P_66,
+#define p_f3 .valid_prefix = P_F3,
+#define p_f2 .valid_prefix = P_F2,
+#define p_00_66 .valid_prefix = P_00 | P_66,
+#define p_00_f3 .valid_prefix = P_00 | P_F3,
+#define p_66_f2 .valid_prefix = P_66 | P_F2,
+#define p_00_66_f3 .valid_prefix = P_00 | P_66 | P_F3,
+#define p_66_f3_f2 .valid_prefix = P_66 | P_F3 | P_F2,
+#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
+
static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
{
if (!s->has_modrm) {
@@ -480,6 +496,23 @@ static bool decode_op(DisasContext *s, CPUX86State *env,
X86DecodedInsn *decode,
return true;
}
+static bool validate_sse_prefix(DisasContext *s, X86OpEntry *e)
+{
+ uint16_t sse_prefixes;
+
+ if (!e->valid_prefix) {
+ return true;
+ }
+ if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
+ /* In SSE instructions, 0xF3 and 0xF2 cancel 0x66. */
+ s->prefix &= ~PREFIX_DATA;
+ }
+
+ /* Now, either zero or one bit is set in sse_prefixes. */
+ sse_prefixes = s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
+ return e->valid_prefix & (1 << sse_prefixes);
+}
+
static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc
decode_func,
X86DecodedInsn *decode)
{
@@ -491,6 +524,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env,
X86DecodeFunc decode_
e->decode(s, env, e, &decode->b);
}
+ if (!validate_sse_prefix(s, e)) {
+ return false;
+ }
+
/* First compute size of operands in order to initialize s->rip_offset. */
if (e->op0 != X86_TYPE_None) {
if (!decode_op_size(s, e, e->s0, &decode->op[0].ot)) {
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 25e5400a8a..8456ae67ad 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -212,6 +212,7 @@ struct X86OpEntry {
X86CPUIDFeature cpuid:8;
unsigned vex_class:8;
X86VEXSpecial vex_special:8;
+ uint16_t valid_prefix:16;
bool is_decode:1;
};
--
2.37.3
- [PATCH v3 00/35] target/i386: new decoder + AVX implementation, Paolo Bonzini, 2022/10/13
- [PATCH 01/35] target/i386: Define XMMReg and access macros, align ZMM registers, Paolo Bonzini, 2022/10/13
- [PATCH 02/35] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/10/13
- [PATCH 05/35] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/10/13
- [PATCH 06/35] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/10/13
- [PATCH 09/35] target/i386: validate SSE prefixes directly in the decoding table,
Paolo Bonzini <=
- [PATCH 04/35] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/10/13
- [PATCH 03/35] target/i386: add core of new i386 decoder, Paolo Bonzini, 2022/10/13
- [PATCH 07/35] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/10/13
- [PATCH 10/35] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/10/13
- [PATCH 16/35] target/i386: Introduce 256-bit vector helpers, Paolo Bonzini, 2022/10/13
- [PATCH 08/35] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/10/13
- [PATCH 13/35] target/i386: support operand merging in binary scalar helpers, Paolo Bonzini, 2022/10/13
- [PATCH 19/35] target/i386: reimplement 0x0f 0x50-0x5f, add AVX, Paolo Bonzini, 2022/10/13
- [PATCH 14/35] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/10/13
- [PATCH 28/35] target/i386: reimplement 0x0f 0x10-0x17, add AVX, Paolo Bonzini, 2022/10/13