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[PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has F
From: |
Peter Maydell |
Subject: |
[PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI |
Date: |
Thu, 25 Apr 2024 11:39:45 +0100 |
From: Jinjie Ruan <ruanjinjie@huawei.com>
If the CPU implements FEAT_NMI, then turn on the NMI support in the
GICv3 too. It's permitted to have a configuration with FEAT_NMI in
the CPU (and thus NMI support in the CPU interfaces too) but no NMI
support in the distributor and redistributor, but this isn't a very
useful setup as it's close to having no NMI support at all.
We don't need to gate the enabling of NMI in the GIC behind a
machine version property, because none of our current CPUs
implement FEAT_NMI, and '-cpu max' is not something we maintain
migration compatibility across versions for. So we can always
enable the GIC NMI support when the CPU has it.
Neither hvf nor KVM support NMI in the GIC yet, so we don't enable
it unless we're using TCG.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com
[PMM: Update comment and commit message]
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index c4b03b09c27..3c93c0c0a61 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -729,6 +729,20 @@ static void create_v2m(VirtMachineState *vms)
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
}
+/*
+ * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
+ * It's permitted to have a configuration with NMI in the CPU (and thus the
+ * GICv3 CPU interface) but not in the distributor/redistributors, but it's
+ * not very useful.
+ */
+static bool gicv3_nmi_present(VirtMachineState *vms)
+{
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
+
+ return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
+ (vms->gic_version != VIRT_GIC_VERSION_2);
+}
+
static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
{
MachineState *ms = MACHINE(vms);
@@ -802,6 +816,11 @@ static void create_gic(VirtMachineState *vms, MemoryRegion
*mem)
vms->virt);
}
}
+
+ if (gicv3_nmi_present(vms)) {
+ qdev_prop_set_bit(vms->gic, "has-nmi", true);
+ }
+
gicbusdev = SYS_BUS_DEVICE(vms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
--
2.34.1
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, (continued)
- [PULL 33/37] hw/char: Implement STM32L4x5 USART skeleton, Peter Maydell, 2024/04/25
- [PULL 12/37] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Peter Maydell, 2024/04/25
- [PULL 09/37] target/arm: Handle PSTATE.ALLINT on taking an exception, Peter Maydell, 2024/04/25
- [PULL 11/37] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Peter Maydell, 2024/04/25
- [PULL 16/37] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Peter Maydell, 2024/04/25
- [PULL 17/37] hw/intc/arm_gicv3: Implement GICD_INMIR, Peter Maydell, 2024/04/25
- [PULL 20/37] hw/intc/arm_gicv3: Implement NMI interrupt priority, Peter Maydell, 2024/04/25
- [PULL 22/37] hw/intc/arm_gicv3: Report the VINMI interrupt, Peter Maydell, 2024/04/25
- [PULL 23/37] target/arm: Add FEAT_NMI to max, Peter Maydell, 2024/04/25
- [PULL 25/37] hw/dma: avoid apparent overflow in soc_dma_set_request, Peter Maydell, 2024/04/25
- [PULL 24/37] hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI,
Peter Maydell <=
- [PULL 27/37] hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr, Peter Maydell, 2024/04/25
- [PULL 28/37] allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset, Peter Maydell, 2024/04/25
- [PULL 32/37] reset: Add RESET_TYPE_SNAPSHOT_LOAD, Peter Maydell, 2024/04/25
- [PULL 34/37] hw/char/stm32l4x5_usart: Enable serial read and write, Peter Maydell, 2024/04/25
- [PULL 35/37] hw/char/stm32l4x5_usart: Add options for serial parameters setting, Peter Maydell, 2024/04/25
- [PULL 31/37] docs/devel/reset: Update to new API for hold and exit phase methods, Peter Maydell, 2024/04/25
- [PULL 36/37] hw/arm: Add the USART to the stm32l4x5 SoC, Peter Maydell, 2024/04/25
- [PULL 30/37] hw, target: Add ResetType argument to hold and exit phase methods, Peter Maydell, 2024/04/25
- [PULL 37/37] tests/qtest: Add tests for the STM32L4x5 USART, Peter Maydell, 2024/04/25
- Re: [PULL 00/37] target-arm queue, Richard Henderson, 2024/04/25