Re: [Qemu-ppc] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.

[Scott Wood]

On 03/22/2012 01:57 PM, Mark Cave-Ayland wrote:
> diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> index 39dcc27..4a21d8d 100644
> --- a/target-ppc/helper.c
> +++ b/target-ppc/helper.c
> @@ -2478,11 +2478,15 @@ static inline void powerpc_excp(CPUPPCState *env, int 
> excp_model, int excp)
>      qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
>                    " => %08x (%02x)\n", env->nip, excp, env->error_code);
>  
> -    /* new srr1 value excluding must-be-zero bits */
> +    /* new srr1 value with interrupt-specific bits defaulting to zero */
>      msr = env->msr & ~0x783f0000ULL;
>  
> -    /* new interrupt handler msr */
> -    new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> +    /* new interrupt handler msr (as per PowerISA 2.06B p.811 and p.814): 
> +       1) force the following bits to zero
> +          IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE
> +       2) default the following bits to zero (can be overidden later on)
> +          RI, HVB (note HVB is a different bit between PPC32/64) */
> +    new_msr = env->msr & ~0xed36ULL & ~((target_ulong) MSR_HVB);

As I think Alex commented recently, we really should be picking the bits
we want to keep rather than the ones we want to exclude.  Please keep in
mind that this code is used by booke as well.  E.g. on booke exceptions
don't normally clear MSR[DE], but it's in your mask of bits to clear.
The mask should depend on both the exception model and the specific
exception type.

It would also be nice to use symbolic names for the MSR bits, rather
than magic hex values (even commented ones).

BTW, The existing MSR[RI] handling also looks wrong -- MSR[RI] should be
preserved rather than set to 1 if it is an exception that does not clear
MSR[RI].

-Scott