Re: [Qemu-ppc] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC interrupt handler.

[Scott Wood]

On 03/23/2012 09:43 PM, David Gibson wrote:
> On Fri, Mar 23, 2012 at 11:34:43AM -0500, Scott Wood wrote:
>> On 03/22/2012 09:20 PM, David Gibson wrote:
>>> On Thu, Mar 22, 2012 at 03:37:49PM -0500, Scott Wood wrote:
>>>> I wonder why this is done again at the end of the function for booke
>>>> (without regard to MSR bits).  It seems like the above flush should
>>>> handle booke as well as classic -- though the comment should be
>>>> "changed/deactivated" rather than "disactivated", since on booke those
>>>> bits just switch from one translation to another.
>>>
>>> Right, which means I don't think this test will work as is for BookE.
>>> There, we'd need to check for any change in the IS/DS bits instead of
>>> just testing presence of IR/DR bits.
>>
>> IS/DS always clear on exceptions, just like IR/DR on classic, so it's
>> the same thing.
> 
> Right, but the semantics are different, which might change when tlb
> flushes are needed.

Flushes are needed when setting the bits as well (probably on both booke
and classic/server -- just because there's no guest-visible translation
doesn't mean the QEMU tlb isn't involved), but that doesn't happen in
this function.  Note that hreg_store_msr() does check for a change in
the bits rather than just whether one was set before.

-Scott