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[Qemu-ppc] [V3 PATCH 7/9] target-ppc: Store Quadword
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [V3 PATCH 7/9] target-ppc: Store Quadword |
Date: |
Mon, 10 Feb 2014 11:26:59 -0600 |
This patch adds support for the Store Quadword instruction in user mode. Prior
to Power ISA 2.07, stq was legal only in privileged mode. Support for Little
Endian mode is also new in ISA 2.07.
Signed-off-by: Tom Musta <address@hidden>
---
V2: Refactored user-mode and Little Endian checks per Alex Graf's review.
target-ppc/translate.c | 39 +++++++++++++++++++++++----------------
1 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1a323dc..f17117e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2995,34 +2995,41 @@ static void gen_std(DisasContext *ctx)
TCGv EA;
rs = rS(ctx->opcode);
- if ((ctx->opcode & 0x3) == 0x2) {
-#if defined(CONFIG_USER_ONLY)
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-#else
- /* stq */
- if (unlikely(ctx->mem_idx == 0)) {
+ if ((ctx->opcode & 0x3) == 0x2) { /* stq */
+
+ bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
+ bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
+
+ if (!legal_in_user_mode && is_user_mode(ctx)) {
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
return;
}
- if (unlikely(rs & 1)) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+
+ if (!le_is_supported && ctx->le_mode) {
+ gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
return;
}
- if (unlikely(ctx->le_mode)) {
- /* Little-endian mode is not handled */
- gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
+
+ if (unlikely(rs & 1)) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_imm_index(ctx, EA, 0x03);
- gen_qemu_st64(ctx, cpu_gpr[rs], EA);
- gen_addr_add(ctx, EA, EA, 8);
- gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
+
+ if (unlikely(ctx->le_mode)) {
+ gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
+ gen_addr_add(ctx, EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_gpr[rs], EA);
+ } else {
+ gen_qemu_st64(ctx, cpu_gpr[rs], EA);
+ gen_addr_add(ctx, EA, EA, 8);
+ gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
+ }
tcg_temp_free(EA);
-#endif
} else {
- /* std / stdu */
+ /* std / stdu*/
if (Rc(ctx->opcode)) {
if (unlikely(rA(ctx->opcode) == 0)) {
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
--
1.7.1
- [Qemu-ppc] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 2/9] target-ppc: Add Target Address SPR (TAR) to Power8, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 1/9] target-ppc: Add Flag for bctar, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 3/9] target-ppc: Add bctar Instruction, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 4/9] target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 8/9] target-ppc: Add Load Quadword and Reserve, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 7/9] target-ppc: Store Quadword,
Tom Musta <=
- [Qemu-ppc] [V3 PATCH 5/9] target-ppc: Add is_user_mode Utility Routine, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 6/9] target-ppc: Load Quadword, Tom Musta, 2014/02/10
- [Qemu-ppc] [V3 PATCH 9/9] target-ppc: Add Store Quadword Conditional, Tom Musta, 2014/02/10
- Re: [Qemu-ppc] [V3 PATCH 0/9] target-ppc: Base ISA V2.07 for Power8, Alexander Graf, 2014/02/20