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[Qemu-ppc] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instru
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instructions |
Date: |
Wed, 12 Feb 2014 15:22:58 -0600 |
This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6ac0486..e2dce90 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6850,6 +6850,9 @@ GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
+GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
+GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
+GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx)
\
@@ -10274,11 +10277,19 @@ GEN_VR_STVE(wx, 0x07, 0x06),
#undef GEN_VX_LOGICAL
#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+
+#undef GEN_VX_LOGICAL_207
+#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+
GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
+GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
+GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
+GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
#undef GEN_VXFORM
#define GEN_VXFORM(name, opc2, opc3) \
--
1.7.1
- [Qemu-ppc] [PATCH 00/28] target-ppc: Altivec 2.07, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Flag, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 02/28] target-ppc: Altivec 2.07: Update AVR Structure, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 03/28] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 04/28] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 05/28] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 06/28] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instructions,
Tom Musta <=
- [Qemu-ppc] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 08/28] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 10/28] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 11/28] target-ppc: Altivec 2.07: vmuluw Instruction, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 13/28] target-ppc: Altivec 2.07: Vector Population Count Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 14/28] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 15/28] target-ppc: Altivec 2.07: Pack Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 17/28] target-ppc: Altivec 2.07: Vector Merge Instructions, Tom Musta, 2014/02/12
- [Qemu-ppc] [PATCH 16/28] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Tom Musta, 2014/02/12