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[Qemu-ppc] [PULL 089/130] target-ppc: Add Load Quadword and Reserve
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 089/130] target-ppc: Add Load Quadword and Reserve |
Date: |
Fri, 7 Mar 2014 00:33:36 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Load Quadword and Reserve (lqarx) instruction,
which is new in Power ISA 2.07.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 1 +
target-ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 365627b..7cf7255 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -926,6 +926,7 @@ struct CPUPPCState {
target_ulong reserve_addr;
/* Reservation value */
target_ulong reserve_val;
+ target_ulong reserve_val2;
/* Reservation store address */
target_ulong reserve_ea;
/* Reserved store source register and size */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 72eff90..13c9802 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3359,6 +3359,42 @@ STCX(stwcx_, 4);
/* ldarx */
LARX(ldarx, 8, ld64);
+/* lqarx */
+static void gen_lqarx(DisasContext *ctx)
+{
+ TCGv EA;
+ int rd = rD(ctx->opcode);
+ TCGv gpr1, gpr2;
+
+ if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
+ (rd == rB(ctx->opcode)))) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
+ return;
+ }
+
+ gen_set_access_type(ctx, ACCESS_RES);
+ EA = tcg_temp_local_new();
+ gen_addr_reg_index(ctx, EA);
+ gen_check_align(ctx, EA, 15);
+ if (unlikely(ctx->le_mode)) {
+ gpr1 = cpu_gpr[rd+1];
+ gpr2 = cpu_gpr[rd];
+ } else {
+ gpr1 = cpu_gpr[rd];
+ gpr2 = cpu_gpr[rd+1];
+ }
+ gen_qemu_ld64(ctx, gpr1, EA);
+ tcg_gen_mov_tl(cpu_reserve, EA);
+
+ gen_addr_add(ctx, EA, EA, 8);
+ gen_qemu_ld64(ctx, gpr2, EA);
+
+ tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
+ tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
+
+ tcg_temp_free(EA);
+}
+
/* stdcx. */
STCX(stdcx_, 8);
#endif /* defined(TARGET_PPC64) */
@@ -9623,6 +9659,7 @@ GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE,
PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
+GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
#endif
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
--
1.8.1.4
- [Qemu-ppc] [PULL 078/130] target-ppc: Update external_htab even when HTAB is managed by kernel, (continued)
- [Qemu-ppc] [PULL 078/130] target-ppc: Update external_htab even when HTAB is managed by kernel, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 082/130] target-ppc: Add Flag for bctar, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 083/130] target-ppc: Add Target Address SPR (TAR) to Power8, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 081/130] target-ppc: Fix xxpermdi When T==A or T==B, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 084/130] target-ppc: Add bctar Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 086/130] target-ppc: Add is_user_mode Utility Routine, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 079/130] qdev: Keep global allocation counter per bus, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 085/130] target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 087/130] target-ppc: Load Quadword, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 091/130] target-ppc: Altivec 2.07: Add Instruction Flag, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 089/130] target-ppc: Add Load Quadword and Reserve,
Alexander Graf <=
- [Qemu-ppc] [PULL 088/130] target-ppc: Store Quadword, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 090/130] target-ppc: Add Store Quadword Conditional, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 073/130] Add Enhanced Three-Speed Ethernet Controller (eTSEC), Alexander Graf, 2014/03/06
[Qemu-ppc] [PULL 092/130] target-ppc: Altivec 2.07: Update AVR Structure, Alexander Graf, 2014/03/06
[Qemu-ppc] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions, Alexander Graf, 2014/03/06
[Qemu-ppc] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Alexander Graf, 2014/03/06