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[Qemu-ppc] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp |
Date: |
Fri, 7 Mar 2014 00:32:50 +0100 |
From: Tom Musta <address@hidden>
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.
The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 13 +++++++++----
target-ppc/helper.h | 1 +
target-ppc/translate.c | 2 ++
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index ac52c23..fec9d1b 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1969,7 +1969,7 @@ VSX_RE(xvresp, 4, float32, f32, 0, 0)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_SQRT(op, nels, tp, fld, sfprf) \
+#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xb; \
@@ -1993,6 +1993,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
} \
} \
\
+ if (r2sp) { \
+ xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+ } \
+ \
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
} \
@@ -2002,9 +2006,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_SQRT(xssqrtdp, 1, float64, f64, 1)
-VSX_SQRT(xvsqrtdp, 2, float64, f64, 0)
-VSX_SQRT(xvsqrtsp, 4, float32, f32, 0)
+VSX_SQRT(xssqrtdp, 1, float64, f64, 1, 0)
+VSX_SQRT(xssqrtsp, 1, float64, f64, 1, 1)
+VSX_SQRT(xvsqrtdp, 2, float64, f64, 0, 0)
+VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0)
/* VSX_RSQRTE - VSX floating point reciprocal square root estimate
* op - instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index b1cf3c0..0192043 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -291,6 +291,7 @@ DEF_HELPER_2(xssubsp, void, env, i32)
DEF_HELPER_2(xsmulsp, void, env, i32)
DEF_HELPER_2(xsdivsp, void, env, i32)
DEF_HELPER_2(xsresp, void, env, i32)
+DEF_HELPER_2(xssqrtsp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0dd6220..13099fc 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7363,6 +7363,7 @@ GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10175,6 +10176,7 @@ GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
+GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
--
1.8.1.4
- [Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions, (continued)
- [Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 018/130] target-ppc: General Support for VSX Helpers, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 112/130] target-ppc: Altivec 2.07: Doubleword Compares, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 042/130] target-ppc: VSX Stage 4: Add xsresp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp,
Alexander Graf <=
- [Qemu-ppc] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 023/130] target-ppc: Add VSX ISA2.06 xsqrt Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 038/130] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 034/130] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Alexander Graf, 2014/03/06