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Re: [Qemu-ppc] [PATCH v2 0/2] Enabling floating point instruction to 440
From: |
Alexander Graf |
Subject: |
Re: [Qemu-ppc] [PATCH v2 0/2] Enabling floating point instruction to 440x5 CPUs |
Date: |
Fri, 12 Sep 2014 21:46:40 +0200 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:31.0) Gecko/20100101 Thunderbird/31.1.1 |
On 12.09.14 21:31, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU in double precision mode.
>
> 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
> 2) Create a new 440x5 implementing floating point instructions
Thanks, applied to ppc-next.
Alex