[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH 50/77] ppc: Update LPCR definitions
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 50/77] ppc: Update LPCR definitions |
Date: |
Wed, 11 Nov 2015 11:28:03 +1100 |
Includes all the bits up to ISA 2.07
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/cpu.h | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index a7236cf..ca6c961 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -493,12 +493,16 @@ struct ppc_slb_t {
#define LPCR_VPM1 (1ull << (63-1))
#define LPCR_ISL (1ull << (63-2))
#define LPCR_KBV (1ull << (63-3))
+#define LPCR_DPFD_SHIFT (63-11)
+#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
+#define LPCR_VRMASD_SHIFT (63-16)
+#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
+#define LPCR_RMLS_SHIFT (63-37)
+#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
#define LPCR_ILE (1ull << (63-38))
-#define LPCR_MER (1ull << (63-52))
-#define LPCR_LPES0 (1ull << (63-60))
-#define LPCR_LPES1 (1ull << (63-61))
#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
+#define LPCR_ONL (1ull << (63-45))
#define LPCR_P7_PECE0 (1ull << (63-49))
#define LPCR_P7_PECE1 (1ull << (63-50))
#define LPCR_P7_PECE2 (1ull << (63-51))
@@ -507,6 +511,12 @@ struct ppc_slb_t {
#define LPCR_P8_PECE2 (1ull << (63-49))
#define LPCR_P8_PECE3 (1ull << (63-50))
#define LPCR_P8_PECE4 (1ull << (63-51))
+#define LPCR_MER (1ull << (63-52))
+#define LPCR_TC (1ull << (63-54))
+#define LPCR_LPES0 (1ull << (63-60))
+#define LPCR_LPES1 (1ull << (63-61))
+#define LPCR_RMI (1ull << (63-62))
+#define LPCR_HDICE (1ull << (63-63))
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
--
2.5.0
- Re: [Qemu-ppc] [PATCH for-2.5 44/77] pci-bridge: Set a supported devfn_min for bridge, (continued)
[Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 47/77] pci: Don't call pci_irq_handler() for a negative intx, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 46/77] pci: Use the new pci_can_add_device() to enforce devfn_min/max, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 43/77] ppc/pnv: Add OCC model stub with interrupt support, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 42/77] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 50/77] ppc: Update LPCR definitions,
Benjamin Herrenschmidt <=
[Qemu-ppc] [PATCH 49/77] ppc/pnv: Create a default PCI layout, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 51/77] ppc: Use a helper to filter writes to LPCR, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 53/77] ppc: Add proper real mode translation support, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 52/77] ppc: Cosmetic, align some comments, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 63/77] ppc: Initialize AMOR in PAPR mode, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 57/77] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 61/77] ppc: SPURR & PURR are HV writeable and privileged, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 55/77] ppc/pnv+spapr: Add "ibm, pa-features" property to the device-tree, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 56/77] ppc: Fix conditions for delivering external interrupts to a guest, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 54/77] ppc: Fix 64K pages support in full emulation, Benjamin Herrenschmidt, 2015/11/10