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Re: [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only |
Date: |
Mon, 16 Nov 2015 16:34:05 +1100 |
User-agent: |
Mutt/1.5.23 (2015-06-09) |
On Wed, Nov 11, 2015 at 11:27:26AM +1100, Benjamin Herrenschmidt wrote:
> Not that anything remotely recent supports tlbia but ...
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> ---
> target-ppc/translate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 10eb9e3..014fe5e 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -4836,7 +4836,7 @@ static void gen_tlbia(DisasContext *ctx)
> #if defined(CONFIG_USER_ONLY)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> - if (unlikely(ctx->pr)) {
> + if (unlikely(ctx->pr || !ctx->hv)) {
If I'm reading your previous patch correctly, ctx->hv won't be set
with in problem state, so I think the ctx->pr check is redundant.
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
> @@ -4850,7 +4850,7 @@ static void gen_tlbiel(DisasContext *ctx)
> #if defined(CONFIG_USER_ONLY)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> - if (unlikely(ctx->pr)) {
> + if (unlikely(ctx->pr || !ctx->hv)) {
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
> @@ -4864,7 +4864,7 @@ static void gen_tlbie(DisasContext *ctx)
> #if defined(CONFIG_USER_ONLY)
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> #else
> - if (unlikely(ctx->pr)) {
> + if (unlikely(ctx->pr || !ctx->hv)) {
> gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
> return;
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 03/77] ppc: Do some batching of TCG tlb flushes, (continued)
- [Qemu-ppc] [PATCH 06/77] ppc: Add macros to register hypervisor mode SPRs, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 19/77] ppc: Fix POWER7 and POWER8 exception definitions, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only, Benjamin Herrenschmidt, 2015/11/10
- Re: [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only,
David Gibson <=
[Qemu-ppc] [PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 20/77] ppc: Fix generation if ISI/DSI vs. HV mode, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 18/77] ppc: Rework POWER7 & POWER8 exception model, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 21/77] ppc: Rework generation of priv and inval interrupts, Benjamin Herrenschmidt, 2015/11/10