Re: [Qemu-ppc] [RFC v2 05/13] target-ppc: add modulo word operations

[Richard Henderson]

On 07/25/2016 04:44 PM, Nikunj A Dadhania wrote:
> Modulo case: a % (b == 0 ? 1 : b)
>
>     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
>     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
>     tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
>     tcg_gen_movi_i32(t3, 0);
>     tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);

No setcond for unsigned; you can do the whole thing with movcond.

  t2 = tcg_const_i32(1);
  t3 = tcg_const_i32(0);
  tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);

But otherwise, yes.

> For "div[wd]o." we will have further cases to implement overflow.

For divwo, you *would* actually do the setcond as above, because that would be 
exactly the overflow condition that you're supposed to compute.

The signed case you pasted looks correct, and the T2 input to the movcond is 
also exactly the overflow condition.


r~